6.5.6. SDI Video Input/Output Ports
The Arria 10 GX FPGA development board includes a SDI video port, which consists of
a M23428G-33 cable driver and a M23544G-14 cable equalizer. The PHY devices from
Macom interface to single-ended SMB connectors.
The cable driver supports operation from 125 Mbps to 11.88 Gbps. Control signals are
allowed for SD and HD modes selections, as well as device enable. The device can be
clocked by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to
incoming signals within 50 ppm using the UP and DN voltage control lines to the
VCXO.
Table 23. SDI Video Output Standards for the SD and HD Input
SD_HD Input Supported Output Standards Rise Time
0 SMPTE 424M, SMPTE 292M Faster
1 SMPTE 259M Slower
Table 24. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and
Functions
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
14 SDI_AVDD — —
2 SDI_AVDD — —
7 SDI_AVDD — —
9 SDI_SD_HDN AW34 1.8 V
5 SDI_TX_RSET — —
1 SDI_TXCAP_N D43 High Speed Differential I/O
16 SDI_TXCAP_P D44 High Speed Differential I/O
10 SDI_TXDRV_N — —
11 SDI_TXDRV_P — —
Table 25. SDI Cable Equalizer Lengths
The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 3.0, 6.0, and 11.88 Gbit dual-link HD
modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-
mute signal interface.
Cable Type
Data Rate (Mbps) Maximum Cable Length (m)
Belden 1694A 270 400
Belden 1694A 1485 140
Belden 1694A 2970 120
Table 26. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and
Functions
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
9 AGCN — —
8 AGXP — —
10 MF0_BYPASS AW32 1.8 V
continued...
6. Board Components
683526 | 2023.07.12
Intel
®
Arria
®
10 FPGA Development Kit User Guide
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