Intel Arria 10 FPGA User Manual

6.7.2. 10/100/1000 Ethernet PHY
The Arria 10 GX FPGA development board supports 10/100/1000 base-T Ethernet
using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore
MAC function. The PHY-to-MAC interface employs SGMII using the Arria 10 GX FPGA
LVDS pins in Soft-CDR mode at 1.25 Gbps transmit and receive. In 10-Mb or 100-Mb
mode, the SGMII interface still runs at 1.25 GHz but the packet data is repeated 10 or
100 times. The MAC function must be provided in the FPGA for typical networking
applications.
The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25 MHz
reference clock driven from a dedicated oscillator. The PHY interfaces to a HALO
HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper
lines with Ethernet traffic.
Figure 33. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
Marvell 10/100/1000 Phy
RJ45 +
Magnetics
MDI Interface SGMII TX/RX
Arria 10 FPGA
Table 31. Ethernet PHY Pin Assignments, Signal Names and Functions
Board Reference
(U15)
Schematic Signal
Name
FPGA Pin Number I/O Standard Description
23 ENET_2P5V_INTN AG13 1.8 V Management bus interrupt
25 ENET_2P5V_MDC AF13 1.8 V Management bus data clock
24 ENET_2P5V_MDIO AL18 1.8 V Management bus data
28 ENET_2P5V_RESE
TN
AW23 1.8 V Device reset
59 ENET_LED_LINK1
0
— 2.5 V 10-Mb link LED
76 ENET_LED_LINK1
0
— 2.5 V 10-Mb link LED
74 ENET_LED_LINK1
00
— 2.5 V 100-Mb link LED
60 ENET_LED_LINK1
000
— 2.5 V 1000-Mb link LED
73 ENET_LED_LINK1
000
— 2.5 V 1000-Mb link LED
58 ENET_LED_RX — 2.5 V RX data active LED
69 ENET_LED_RX — 2.5 V RX data active LED
68 ENET_LED_TX — 2.5 V TX data active LED
30 ENET_RSET AW23 1.8 V Device reset
75 ENET_RX_N AW24 LVDS SGMII receive channel
continued...
6. Board Components
683526 | 2023.07.12
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10 FPGA Development Kit User Guide
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Intel Arria 10 FPGA Specifications

General

Brand	Intel
Model	Arria 10 FPGA
Category	Microcontrollers
Language	English