Intel Arria 10 FPGA - Page 21

The BTS communicates over the JTAG bus to a test design running in the FPGA. The
Board Test System and Power Monitor share the JTAG bus with other applications like
the Nios II debugger and the SignalTap
®
II Embedded Logic Analyzer. Because the
BTS is designed based on the Quartus Programmer and System Console, be sure to
close other applications before you use the BTS application.
4. Board Test System
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10 FPGA Development Kit User Guide
21