Intel Arria 10 FPGA User Manual

Control Description
QSFP x4
SFP x1
SMA x1
SDI x1
PMA Setting Allows you to make changes to the PMA parameters that affect the active transceiver
interface. The following settings are available for analysis:
Serial Loopback—Routes signals between the transmitter and the receiver.
VOD—Specifies the voltage output differential of the transmitter buffer.
Pre-emphasis tap
• 1st pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
• 2nd pre—Specifies the amount of pre-emphasis on the second pre-tap of the
transmitter buffer.
• 1st post—Specifies the amount of pre-emphasis on the first post tap of the transmitter
buffer.
• 2nd post—Specifies the amount of pre-emphasis on the second post tap of the
transmitter buffer.
Equalizer—Specifies the AC gain setting for the receiver equalizer in four stage mode.
DC gain—Specifies the DC gain setting for the receiver equalizer in four stage mode.
VGA—Specifies the VGA gain value.
All PMA settings should be changed as in Figure 20 on page 33.
Data Type Specifies the type of data contained in the transactions. The following data types are
available for analysis:
• PRBS 7—Selects pseudo-random 7-bit sequences.
• PRBS 15—Selects pseudo-random 15-bit sequences.
• PRBS 23—Selects pseudo-random 23-bit sequences.
• PRBS 31—Selects pseudo-random 31-bit sequences.
• HF—Selects highest frequency divide-by-2 data pattern 10101010.
• LF—Selects lowest frequency divide by 33 data pattern.
Error Control Displays data errors detected during analysis and allows you to insert errors:
• Detected errors—Displays the number of data errors detected in the hardware.
• Inserted errors—Displays the number of errors inserted into the transmit data stream.
• Insert Error—Inserts a one-word error into the transmit data stream each time you click
the button. Insert Error is only enabled during transaction performance analysis.
• Clear—Resets the Detected errors and Inserted errors counters to zeroes.
Loopback Start—Initiates the selected ports transaction performance analysis.
Note: Always click Clear before Start.
Stop—Terminates transaction performance analysis.
TX and RX performance bars—Show the percentage of maximum theoretical data rate that
the requested transactions are able to achieve.
4. Board Test System
683526 | 2023.07.12
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10 FPGA Development Kit User Guide
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Intel Arria 10 FPGA Specifications

General

Brand	Intel
Model	Arria 10 FPGA
Category	Microcontrollers
Language	English