Keithley 2016 - Figure 4-6 Standard Event Status

An enable register is not cleared when it is read. The following operations affect the enable
registers:
• Cycling power - Clears all enable registers
• :STATus:PREset clears the following enable registers:
Operation Event Enable Register
Questionable Event Enable Register
Measurement Event Enable Register
*ESE 0 - Clears the Standard Event Status Enable Register.
* ESR ?
PON
(B7)
URQ
(B6)
CME
(B5)
EXE
(B4)
DDE
(B3)
QYE
(B2) (B1) (B0)
OR
Standard Event
Status Register
Standard Event
Status Enable
Register
PON = Power On
URQ = User Request
CME = Command Error
EXE = Execution Error
DDE = Device-Dependent Error
QYE = Query Error
OPC = Operation Complete
& = Logical AND
OR = Logical OR
&
&
&
&
&
OPC
&
&
PON
(B7)
URQ
(B6)
CME
(B5)
EXE
(B4)
DDE
(B3)
QYE
(B2) (B1) (B0)
OPC
* ESE
* ESE ?
To Event
Summary
Bit (ESB) of
Status Byte
Register (See
Figure 4-10).
(B15 - B8)
(B15 - B8)
Fi
gure
4
-
6
Standard event status
4-18 Remote Operation