Keysight MP4300 Series User Manual

Bit Bit Name Decimal Value Definition
0 OT_PFC 1 An over-temperature occurred in the PFC
1 OT_FPGA 2 An over-temperature occurred in the main FPGA
2 OT_CPU 4 An over-temperature occurred in the main processor
3 FAN 8 The fans have either stopped running or are running too slow
4 LOB 16 The Lockout bar is not installed in the mainframe
5 POW_FAIL 32 The input power is outside the specified operating range
6 - 8 not used not used 0 is returned
Status Byte Register
This register summarizes the information from all other status groups as defined in the IEEE 488.2
Standard Digital Interface for Programmable Instrumentation. Refer to Status Diagram.
The following table describes the Status Byte register bit assignments.
Bit Bit Name Decimal Value Definition
0 Questionable2 Status
Summary
1 One or more bits are set in the Questionable2 Data Register. Bits
must be enabled, see STATus:QUEStionable:ENABle
1 not used not used 0 is returned
2 Error Queue 4 One or more errors in the Error Queue. Use SYSTem:ERRor? to read
and delete errors.
3 Questionable Status
Summary
8 One or more bits are set in the Questionable Data Register. Bits must
be enabled, see STATus:QUEStionable:ENABle.
4 Message Available 16 Data is available in the instrument's output buffer.
5 Event Status
Summary
32 One or more bits are set in the Standard Event Register. Bits must be
enabled, see *ESE.
6 Master Status
Summary
64 One or more bits are set in the Status Byte Register and may gen-
erate a Request for Service. Bits must be enabled, see *SRE.
7 Operation Status
Summary
128 One or more bits are set in the Operation Status Register. Bits must
be enabled, see STATus:OPERation:ENABle.
Master Status Summary and Request for Service Bits
MSS is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service
Request Enable register. MSS is set whenever the instrument has one or more reasons for requesting
service. *STB? reads the MSS in bit position 6 of the response but does not clear any of the bits in the
Status Byte register.
The RQS bit is a latched version of the MSS bit. Whenever the instrument requests service, it sets the
SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller does
a serial poll, RQS is cleared inside the register and returned in bit position 6 of the response. The
remaining bits of the Status Byte register are not disturbed.
Keysight MP4300 Series Operating and Service Guide 151
5 SCPI Programming Reference

Keysight MP4300 Series Specifications

General

Brand	Keysight
Model	MP4300 Series
Category	Power Supply
Language	English