STATus:QUESt<1|2>:ENABle <value>, (@<chanlist>)
STATus:QUESt<1|2>:ENABle? (@<chanlist>)
Sets the value of the enable register for the Questionable Status group. The enable register is a mask
for enabling specific bits from the Operation Event register to set the QUES (questionable summary) bit
of the Status Byte register. STATus:PRESet clears all bits in the enable register.
Parameter Typical Return
A decimal value corresponding to the binary-weighted sum of
the register's bits.
<bit value>
<chanlist> one or more channels
Enable bit 2 and 4 in the questionable enable register #1: STAT:QUES1:ENAB 20, (@1
l
For example, with bit 2 (value 4) and bit 4 (value 16) set, the query returns +20.
l
*CLS does not clear the enable register, but does clear the event register.
STATus:QUESt<1|2>:NTRansition <value>, (@<chanlist>)
STATus:QUESt<1|2>:NTRansition? (@<chanlist>)
STATus:QUESt<1|2>:PTRansition <value>, (@<chanlist>)
STATus:QUESt<1|2>:PTRansition? (@<chanlist>)
Sets and queries the value of the NTR (Negative-Transition) and PTR (Positive-Transition) registers.
These serve as a polarity filter between the Questionable Condition and Questionable Event registers.
When a bit in the NTR register is set to 1, then a 1-to-0 transition of the corresponding bit in the
Questionable Condition register causes that bit in the Questionable Event register to be set.
When a bit in the PTR register is set to 1, then a 0-to-1 transition of the corresponding bit in the
Questionable Condition register causes that bit in the Questionable Event register to be set.
STATus:PRESet sets all bits in the PTR registers and clears all bits in the NTR registers.
Parameter Typical Return
A decimal value corresponding to the binary-weighted sum of
the register's bits.
<bit value>
<chanlist> one or more channels
Enable bit 3 and 4 in the questionable NTR register #1: STAT:QUES1:NTR 24, (@1
Enable bit 3 and 4 in the questionable PTR register #1: STAT:QUES1:PTR 24, (@1
l
If the same bits in both NTR and PTR registers are set to 1, then any transition of that bit at the
Questionable Condition register sets the corresponding bit in the Questionable Event register.
l
If the same bits in both NTR and PTR registers are set to 0, then no transition of that bit at the Ques-
tionable Condition register can set the corresponding bit in the Questionable Event register.
l
The value returned is the binary-weighted sum of all enabled bits in the register.
Keysight MP4300 Series Operating and Service Guide 137
5 SCPI Programming Reference
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