Micom P631 - Page 385

Parameter Address
Default Min Max Unit Logic Diagram
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CBF_2: Latching trip cmd.t1
022 225
0: No
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The 1st timer stage trip command, set to latch mode, will remain active until
reset by operating parameters or through an appropriately configured binary
signal input.
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CBF_1: Latching trip cmd.t2
022 170
0: No Fig. 3-132, (p. 3-164)
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CBF_2: Latching trip cmd.t2
022 226
0: No
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The 2nd timer stage trip command, set to latch mode, will remain active until
reset by operating parameters or through an appropriately configured binary
signal input.
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CBF_1: Delay/starting trig.
022 155
0.00 0.00 100.00 s Fig. 3-133, (p. 3-165)
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CBF_2: Delay/starting trig.
022 220
0.00 0.00 100.00 s
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The signal CBF_1: Trip signal (or CBF_2: Trip signal, . . ., resp.) is
issued when this timer stage's time duration has elapsed.
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CBF_1: Delay/fault beh. CB
022 171
0.12 0.00 100.00 s Fig. 3-134, (p. 3-165)
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CBF_2: Delay/fault beh. CB
022 227
0.12 0.00 100.00 s
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If during this delay time period the circuit breaker does not provide a signal from
its auxiliary contacts that it is closed, then faults behind the CB are recognized
through the current criterion (see section “Fault behind CB protection”).
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CBF_1: Delay/CB sync.superv
022 172
Blocked 0.00 100.00 s Fig. 3-135, (p. 3-166)
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CBF_2: Delay/CB sync.superv
022 218
Blocked 0.00 100.00 s
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Setting for the time delay to bridge circuit breaker operate times during CB
synchronization supervision.
7 Settings
P631
P631/EN M/R-11-C // P631-310-650 7-85