Mitsubishi Electric Q173DSCPU - Page 188

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3 MOTION DEDICATED PLC INSTRUCTION
(c) CPU dedicated instruction transmission area
If the size of the CPU dedicated instruction transmission area is insufficient,
it can be increased changing the system area size. The size of the CPU
dedicated instruction transmission area is decided depending on the number
of CPU modules used and selected system area size as follows.
Refer to the "Q173D(S)CPU/Q172D(S)CPU Motion controller Programming
Manual (COMMON)" for details of the system area size change.
• Number of Multiple CPU modules: 2
Selected system
area size
Number of CPU dedicated instruction transmission area
for each target CPU
1k word 47 blocks
2k word 111 blocks
• Number of Multiple CPU modules: 3
Selected system
area size
Number of CPU dedicated instruction transmission area
for each target CPU
1k word 23 blocks
2k word 55 blocks
• Number of Multiple CPU modules: 4
Selected system
area size
Number of CPU dedicated instruction transmission area
for each target CPU
1k word 15 blocks
2k word 36 blocks
(d) Number of simultaneous instruction acceptance for Motion CPU
The following number of instructions can be accepted simultaneously in the
Motion CPU.
• D(P).SFCS : 64
• Total of D(P).SVST, D(P).CHGA and D(P).CHGAS
QDS
:
• Q173DSCPU/Q173DSCPU : 128
(Note-1)
• Q173DCPU(-S1)/Q173DCPU(-S1) : 64
(Note-1): 64 for operating system software version "00A".
• D(P).GINT : 32
• Total of D(P).DDRD and D(P).DDWR : 64
• D(P).CHGV/D(P).CHGVS
QDS
/D(P).CHGT/D(P).CHGT2
QDS
: Last instruction for each axis executed is valid. There is not a
limitation for number of simultaneous instruction acceptance.
When more than the above number of instructions are executed by the PLC
CPU, even if there is enough area in the CPU dedicated instruction
transmission area, the Motion CPU cannot accept it.
In this case, 2100 is set to the complete status information and it abnormal
completion occurs.