Figure 45 System power-up sequence
Clocking scheme
There are two main clocks in the system:
• 38.4MHz RF clock produced by VCTCXO in RF section
• 32.768kHz sleep clock produced by the EM ASIC AVILMA (N2200) with an external crystal.
RF clock is generated only when VCTCXO is powered on by the EM ASIC regulator. The regulator itself is
activated by SleepX signal from RAPIDOYawe (D2800). When both CPU’s are on sleep, RF clock is stopped.
RM-247
System Module
Page 7 –10 COMPANY CONFIDENTIAL Issue 1
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