Nvidia JETSON XAVIER NX Design Guide

Miscellaneous Interfaces
NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 70
12.2 SPI
The Jetson Xavier NX brings out two of the Xavier SPI interfaces. See Figure 12-2.
Table 12-4. SPI Pin Descriptions
Pin #
Module Pin
Name
Xavier Signal Usage/Description
Recommended
Usage
Directio
n
Pin Type
91 SPI0_SCK SPI1_SCK SPI 0 Clock
SPI #0 Device
#0 or #1
Bidir
CMOS –
1.8V
93 SPI0_MISO SPI1_MISO SPI 0 Initiator In / Target Out
89 SPI0_MOSI SPI1_MOSI SPI 0 Initiator Out / Target In
95 SPI0_CS0* SPI1_CS0 SPI 0 Chip Select 0
SPI #0 Device
#0
97 SPI0_CS1* SPI1_CS1 SPI 0 Chip Select 1
SPI #0 Device
#1
106 SPI1_SCK SPI3_SCK SPI 1 Clock
SPI #1 Device
#0 or #1
108 SPI1_MISO SPI3_MISO SPI 1 Initiator In / Target Out
104 SPI1_MOSI SPI3_MOSI SPI 1 Initiator Out / Target In
110 SPI1_CS0* SPI3_CS0 SPI 1 Chip Select 0
SPI #1 Device
#0
112 SPI1_CS1* SPI3_CS1 SPI 1 Chip Select 1
SPI #1 Device
#1
Notes: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals.
Figure 12-2. SPI Connections
Jetson
SoC – SPI
UART
SPI0_SCK
SP I0_M I SO
SP I0_M OSI
SP I0_C S0*
SP I0_C S1*
SPI1_SCK
SP I_MISO
SP I1_M OSI
SP I1_C S0*
SP I1_C S1*
SPI1_SCK
SPI1_MISO
SPI1_MOSI
SPI1_CS0
SPI1_CS1
Connect to up to 2 SPI
devices (separate CS
for each)
91
89
93
95
97
SPI3_SCK
SPI3_MISO
SPI3_MOSI
SPI3_CS0
SPI3_CS1
106
104
108
110
112
Connect to up to 2 SPI
devices (separate CS
for each)

Nvidia JETSON XAVIER NX Specifications

General

Storage	16 GB eMMC 5.1
AI Performance	21 TOPS (INT8)
Operating Temperature	-25°C to 80°C
Operating System	Linux (JetPack SDK)
GPU	NVIDIA Volta architecture with 384 CUDA cores and 48 Tensor cores
CPU	6-core NVIDIA Carmel ARMv8.2 64-bit CPU 6 MB L2 + 4 MB L3
Memory	8GB 128-bit LPDDR4x
Video Decode	2x 4K60 | 4x 4K30 | 8x 1080p60 | 16x 1080p30 (H.265/H.264)
Camera	Up to 6 cameras
Connectivity	Gigabit Ethernet, M.2 Key E for Wi-Fi/Bluetooth
Power	10 W / 15 W / 20 W
Dimensions	70mm x 45mm