Nvidia JETSON XAVIER NX

Miscellaneous Interfaces
NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 71
Figure 12-3 shows the basic connections used.
Figure 12-3. Basic SPI Initiator and Target Connections
Jetson Initiator
SPIn_CSx
SP In_SCK
SP In_MOSI
SP In_MISO
SPI Target Device
CS (Chip Select)
CLK ( Clock)
MOSI (Initiator out, Target in)
MISO (Initiator in, Target out)
Jetson Target
SPIn_CSx
SP In_SCK
SP In_MOSI
SP In_MISO
SPI Initiator Device
CS (Chip Select)
CLK ( Clock)
MOSI (Initiator out, Target in)
MISO (Initiator in, Target out)
12.2.1 SPI Design Guidelines
The following guidelines meet the SPI design guidelines.
Figure 12-4. SPI Topologies
Jetson
SPI
Device
#1
Main trunk
SPI
Device
#2
SPI
Device
#1
Main trunk
SPI
Device
#2
Branch-A
Branch-B
Branch-A
Branch-B
2x-Load Star Topology 2x-Load Daisy Topology
SPI
Device
Main trunk
SoC
Jetson
SoC
Jetson
SoC
Point-Point Topology
Table 12-5. SPI Interface Signal Routing Requirements
Parameter
Requirement
Units
Notes
Max frequency
65
MHz
Configuration / device organization
4
load
Max loading (total of all loads)
15
pF
Reference plane
GND
Breakout region impedance
Minimum width
and spacing
Max PCB breakout delay
75
ps
Trace impedance
50 – 60
Ω
±15%
Via proximity (signal to reference)
< 3.8 (24)
mm (ps)
See Note 1
Trace spacing: Microstrip / Stripline
4x / 3x
dielectric
Max trace length/delay (PCB main trunk) For MOSI, MISO, SCK
and CS
Point-point
2x-load star/daisy
195 (1228)
120 (756)
mm (ps)
Max trace length/delay (Branch-A) for MOSI, MISO, SCK and CS
2x-load star/daisy 75 (472)
mm (ps)
Max trace length/delay skew from MOSI, MISO and CS to SCK
16 (100)
mm (ps)
At any point
Note
: Up to four signal vias can share a single GND return via