USB and PCIe
NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 29
6.2.1 PCIe Design Guidelines
The following tables provide the PCIe routing guidelines for the PCIe #1 (x1) or PCIe #0 (x4)
interfaces. PCIe #1 supports up to Gen3 and the first table applies. PCIe #0 supports up to
Gen4 and if the design will need to operate at Gen4 speed, the second routing table applies.
Table 6-9. PCIe Interface Signal Routing Requirements to Gen3
4.0GHz, half-rate architecture
Configuration / Device Organization
Unidirectional, differential
To GND Single Ended for P & N
Trace Impedance differential / Single
Ended
Trace Spacing (Stripline/Microstrip)
Pair – Pair
To plane and capacitor pad
To unrelated high-speed signals
3x / 4x
3x / 4x
Dielectric
TX and RX should not be routed on the
same layer. See Note 2.
Trace loss budget (for carrier board routing)
Routing direct to device
Routing to PCIe/M.2 connector
-11.5
-7.5
dB
@ 4GHz (See Figure 6-3),
Loss: GEN3 budget – module – end
device – safety margin (-22dB + 3.5dB +
4dB + 3dB)
Loss: GEN3 budget – module – end
device – safety margin (-22dB + 3.5dB +
Breakout region (Max Length)
Minimum width and spacing. 4x or
wider dielectric height spacing is
preferred
Direct to device on carrier board
Stripline
Microstrip
Routed to PCIe or M.2 connector
Stripline
15.3 (2680)
14.4 (2160)
10 (1750)
in (ps)
Mid-loss PCB of 0.8dB/in (Microstrip) or
0.75dB/in (Stripline) is used. Also,
175ps/in for Stripline routing and
150ps/in for Microstrip.
Max PCB via distance from the BGA
Max distance from BGA ball to first PCB
via.
PCB within pair (intra-pair) skew
Do trace length matching before hitting
discontinuities. See notes 3 and 4.
Within pair (intra-pair) matching between
subsequent discontinuities
Differential pair uncoupled length
Place GND vias as symmetrically as possible to data pair vias. GND via distance
should be placed less than 1x the diff pair via pitch
PTH Vias
2 for TX traces and 2 for RX trace
Longer via stubs would require review
Routing signals over antipads