EasyManua.ls Logo

NXP Semiconductors MPC5746R - Page 96

NXP Semiconductors MPC5746R
98 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Table 61. Revision history (continued)
Revision Date Description of changes
In Table 19 :
In the SNR, THD, SINAD, and ENOB rows Conditions, changed "50 kHz" to "125 kHz".
Modified footnote to ENOB
In IDD_VDDA and IDD_VDDR rows, modified values.
In VBG_REF row's Conditions, added "INPSAMP=0xFF"
Added NOTE "For spec complaint operation, do not expose clock sources, including crystal
oscillator, IRC, PLL0, and PLL1 on the CLKOUT pads while the SAR ADC is converting."
Added NOTE: "The ADC performance specifications are not guaranteed if two or more ADCs
simultaneously sample the same shared channel".
In section S/D ADC :
In Table 20 :
For THD
DIFF333
GAIN = 16, updated Min value.
For I
ADV_D
, updated Max value.
In section LFAST and MSC /DSPI LVDS interface electrical characteristics :
After table Table 24 added NOTE "For optimum LVDS performance, it is recommended to set
the neighbouring GPIO pads to use Weak Drive".
In section Device voltage monitoring :
In Table 29 :
For LVD_core_hot, LVD_HV, and LVD_IO specs, removed the untrimmed Rising
voltage and Falling voltage rows.
For LVD_core_hot, changed Mask Opt. value to "No".
In section Regulator example for the 2SCR574d transistor, figure "Regulator example", changed “5V
or Vcollector” to “3.3V or Vcollector”.
In section DSPI CMOS master mode – classic timing, Table 40 :
Changed tSDC spec's Condition SCK drive strength from "0 pF" to "0 to 50 pF".
In tSUI and tHI specs' footnote, removed reference to "Automotive" thresholds.
In section DSPI CMOS master mode – modified timing, Table 41 :
Changed tSDC spec's Condition SCK drive strength from "0 pF" to "0 to 50 pF".
In tSUI and tHI specs' footnote, removed reference to "Automotive" thresholds.
In section DSPI master mode – output only, Table 44, changed tSDC spec's Condition SCK drive
strength from "0 pF" to "0 to 50 pF".
Added section eMIOS timing.
In section Ordering information, Table 60 :
Updated Part Numbers.
Updated Emulation device footnote.
4
03/2016 In section Block diagram, Figure 2 :
"DECIM" changed to "DECFILTER".
"SIPI" changed to "Zipwire".
I/O lines added to Zipwire, SIUL2, REACM, eTPU, eMIOS, IGF, and XOSC.
In section Absolute maximum ratings table "Absolute maximum ratings", removed I
IOMAX
spec and
added I
MAXSEG
spec.
In section Operating conditions table "Device operating conditions":
For the FEC I/O supply voltage, MSC I/O supply voltage, and JTAG I/O supply voltage specs,
removed the LVD enabled/disabled distinction.
Added footnote to I
MAXSEG
.
In section I/O pad current specifications :
Table continues on the next page...
Revision history
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
96 NXP Semiconductors

Table of Contents

Other manuals for NXP Semiconductors MPC5746R

Related product manuals