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CJ1-H-R, CJ1-H, CJ1M, and CJ1 CPU Unit Comparison Section 1-7
Execution
timing
CPU execution process-
ing modes
Any of the following four modes:
1. Normal (instructions and peripheral servicing per-
formed consecutively)
2. Peripheral Servicing Priority Mode (instruction execu-
tion interrupted to service peripherals at a specific
cycle and time; consecutive refreshing also per-
formed)
3. Parallel Processing Mode with Synchronous Memory
Access (instruction executed and peripheral services
in parallel while synchronizing access to I/O memory)
4. Parallel Processing Mode with Asynchronous Memory
Access (instruction executed and peripheral services
in parallel without synchronizing access to I/O mem-
ory)
Either of following two modes:
1. Either of following two modes: Normal
(instructions and peripheral servicing
performed consecutively)
2. Peripheral Servicing Priority Mode
(instruction execution interrupted to
service peripherals at a specific cycle
and time; consecutive refreshing also
performed)
CPU Bus
Unit spe-
cial
refreshing
Data links During I/O refresh period or via special CPU BUS UNIT I/O REFRESH instruc-
tion (DLNK(226))
During I/O
refresh period
DeviceNet
remote I/O
Protocol
macro
send/
receive
data
Refreshing of CIO and
DM Areas words allo-
cated to CPU Bus Unit
Tasks Cyclic execution of
interrupt tasks via
TKON instruction
(called “extra cyclic
tasks”)
Supported.
(Up to 256 extra cyclic tasks, increasing the total number of cyclic tasks to 288
max.)
Not supported.
(No extra cyclic
tasks; 32 cyclic
tasks max.)
Independent/shared
specifications for index
and data registers
Supported.
The time to switch between tasks can be reduced if shared registers are used.
Not supported.
(Only indepen-
dent registers for
each task.)
Initialization when tasks
are started
Supported.
Task Startup Flags supported.
Only Task Flag
for first execu-
tion.
Starting subroutines
from multiple tasks
Global subroutines can be defined that can be called from more than one task. Not supported.
Scheduled interrupt
interval for scheduled
interrupt tasks
0.2 ms to 999.9 ms
(in increments of
0.1 ms), 1 ms to
9,999 ms (in incre-
ments of 1 ms), or
10 ms to 99,990
ms (in increments
of 10 ms)
1 ms to 9,999 ms (in increments of
1 ms) or 10 ms to 99,990 ms (in
increments of 10 ms)
0.5 ms to 999.9 ms
(in increments of
0.1 ms), 1 ms to
9,999 ms (in incre-
ments of 1 ms), or
10 ms to 99,990 ms
(in increments of
10 ms)
1 ms to 9,999 ms
(in increments of
1 ms) or 10 ms
to 99,990 ms (in
increments of
10 ms)
Interrupt
task execu-
tion timing
during
instruction
execution
For
instruc-
tions other
than the
following
ones
Any instruction that is being executed is interrupted when interrupt task conditions are met to start
the interrupt task. If the cyclic task (including extra cyclic tasks) accesses the same data area
words as the instruction that was interrupted, data may not be concurrent. To ensure data concur-
rency, the DI and EI instructions must be used to disable and enable interrupts during a specific
part of the program.
For BIT
COUNTE
R (BCNT)
or BLOCK
TRANS-
FER
(XFER)
instruc-
tions
Interrupt tasks are started only after execution of the instruction has been com-
pleted, ensuring data concurrency even when the same data area words are
accessed from the instruction and the interrupt task.
Debug-
ging
Backup to Memory
Cards (simple backup
function)
In addition to the data listed at the right, data from Units mounted to the CPU
Rack or Expansion Racks can also be backed up to the Memory Card (via push-
button on front panel). This is very effective when replacing Units. Backup data
includes scan lists for DeviceNet Units, protocol macros for Serial Communica-
tions Units, etc.
Only the user
program, param-
eters, and I/O
memory in the
CPU Unit.
Automatic user program
and parameter area
backup to flash memory
Supported (enabling battery-free operation without a Memory Card)
The user program and parameter area data are automatically backed up the
flash memory whenever they are transferred to the CPU Unit from the CX-Pro-
grammer, file memory, etc.
Not supported.
Item CJ1-H-R CPU
Unit
CJ1-H CPU Unit CJ1M CPU Unit CJ1 CPU Unit
CJ1H-CPU6@H-R CJ1H-CPU6@H CJ1G-CPU4@H CJ1M-CPU2@/1@ CJ1G-CPU4@
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