EasyManua.ls Logo

Omron CJ - 08-2008 - Sequence Control Instructions; Sequence Output Instructions

Omron CJ - 08-2008
733 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
474
Instruction Execution Times and Number of Steps Section 10-5
10-5-2 Sequence Output Instructions
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
10-5-3 Sequence Control Instructions
Instruction Mnemonic Code Length
(steps)
(See
note.)
ON execution time (µs) Conditions
CPU6@H-R CPU6@HCPU4@HCPU4@ CJ1M
excluding
CPU11/21
CJ1M
CPU11/21
OUTPUT OUT --- 1 0.016 0.02 0.04 0.21 0.35 0.35 ---
!OUT --- 2 +21.37 +21.37 +21.37 +21.37 +23.07 +28.60 Increase for imme-
diate refresh
OUTPUT NOT OUT NOT --- 1 0.016 0.02 0.04 0.21 0.35 0.35 ---
!OUT NOT --- 2 +21.37 +21.37 +21.37 +21.37 +23.07 +28.60 Increase for imme-
diate refresh
KEEP KEEP 011 1 0.048 0.06 0.08 0.29 0.40 0.40 ---
DIFFERENTIATE
UP
DIFU 013 2 0.21 0.24 0.40 0.54 0.50 0.50 ---
DIFFERENTIATE
DOWN
DIFD 014 2 0.21 0.24 0.40 0.54 0.50 0.50 ---
SET SET --- 1 0.016 0.02 0.06 0.21 0.30 0.30 ---
!SET --- 2 +21.37 +21.37 +21.37 +21.37 +23.17 +28.60 Increase for imme-
diate refresh
RESET RSET --- 1 0.016 0.02 0.06 0.21 0.30 0.30 Word specified
!RSET --- 2 +21.37 +21.37 +21.37 +21.37 +23.17 +28.60 Increase for imme-
diate refresh
MULTIPLE BIT
SET
SETA 530 4 5.8 5.8 6.1 7.8 11.8 11.8 With 1-bit set
25.7 25.7 27.2 38.8 64.1 64.1 With 1,000-bit set
MULTIPLE BIT
RESET
RSTA 531 4 5.7 5.7 6.1 7.8 11.8 11.8 With 1-bit reset
25.8 25.8 27.1 38.8 64.0 64.0 With 1,000-bit reset
SINGLE BIT SET SETB 532 2 0.19 0.24 0.34 --- 0.5 0.5 ---
!SETB 3 +21.44 +21.44 +21.54 --- +23.31 +23.31 ---
SINGLE BIT
RESET
RSTB 533 2 0.19 0.24 0.34 --- 0.5 0.5 ---
!RSTB 3 +21.44 +21.44 +21.54 --- +23.31 +23.31 ---
SINGLE BIT OUT-
PUT
OUTB 534 2 0.19 0.22 0.32 --- 0.45 0.45 ---
!OUTB 3 +21.42 +21.42 +21.52 --- +23.22 +23.22 ---
Instruction Mnemonic Code Length
(steps)
(See
note 1.)
ON execution time (
µs) Conditions
CPU6@H-R CPU6@HCPU4@HCPU4@ CJ1M
excluding
CPU11/21
CJ1M
CPU11/21
END END 001 1 5.5 5.5 6.0 4.0 7.9 7.9 ---
NO OPERATION NOP 000 1 0.016 0.02 0.04 0.12 0.05 0.05 ---
INTERLOCK IL 002 1 0.048 0.06 0.06 0.12 0.15 0.15 ---
INTERLOCK
CLEAR
ILC 003 1 0.048 0.06 0.06 0.12 0.15 0.15 ---
MULTI-INTER-
LOCK DIFFEREN-
TIATION HOLD
(See note 2.)
MILH 517 3 6.1 6.1 6.5 --- 10.3 11.7 During interlock
7.5 7.5 7.9 --- 13.3 14.6 Not during interlock
and interlock not set
8.9 8.9 9.7 --- 16.6 18.3 Not during interlock
and interlock set
MULTI-INTER-
LOCK DIFFEREN-
TIATION
RELEASE (See
note 2.)
MILR 518 3 6.1 6.1 6.5 --- 10.3 11.7 During interlock
7.5 7.5 7.9 --- 13.3 14.6 Not during interlock
and interlock not set
8.9 8.9 9.7 --- 16.6 18.3 Not during interlock
and interlock set
MULTI-INTER-
LOCK CLEAR
(See note 2.)
MILC 519 2 5.0 5.0 5.6 --- 8.3 12.5 Interlock not cleared
5.7 5.7 6.2 --- 9.6 14.2 Interlock cleared
JUMP JMP 004 2 0.31 0.38 0.48 8.1 0.95 0.95 ---
JUMP END JME 005 2 --- --- --- --- --- --- ---
CONDITIONAL
JUMP
CJP 510 2 0.31 0.38 0.48 7.4 0.95 0.95 When JMP condi-
tion is satisfied

Table of Contents

Related product manuals