493
Instruction Execution Times and Number of Steps Section 10-5
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
CONDITIONAL
BLOCK EXIT
(Execution
condition)
EXIT
806 1 10.0 10.0 11.3 12.9 23.8 26.0 EXIT condition sat-
isfied
4.0 4.0 4.9 7.3 7.2 8.4 EXIT condition not
satisfied
CONDITIONAL
BLOCK EXIT
EXIT (bit
address)
806 2 6.8 6.8 13.5 16.3 28.4 30.6 EXIT condition sat-
isfied
4.7 4.7 7.2 10.7 11.4 13.1 EXIT condition not
satisfied
CONDITIONAL
BLOCK EXIT
(NOT)
EXIT NOT
(bit
address)
806 2 12.4 12.4 14.0 16.8 28.4 31.2 EXIT condition sat-
isfied
7.1 7.1 7.6 11.2 11.8 13.5 EXIT condition not
satisfied
Branching IF (execu-
tion condi-
tion)
802 1 4.6 4.6 4.8 7.2 6.8 8.5 IF true
6.7 6.7 7.3 10.9 12.2 13.9 IF false
Branching IF (relay
number)
802 2 6.8 6.8 7.2 10.4 11.0 12.7 IF true
9.0 9.0 9.6 14.2 16.5 18.5 IF false
Branching (NOT) IF NOT
(relay num-
ber)
802 2 7.1 7.1 7.6 10.9 11.5 13.1 IF true
9.2 9.2 10.1 14.7 16.8 18.9 IF false
Branching ELSE 803 1 6.2 6.2 6.7 9.9 11.4 12.6 IF true
6.8 6.8 7.7 11.2 13.4 15.0 IF false
Branching IEND 804 1 6.9 6.9 7.7 11.0 13.5 15.4 IF true
4.4 4.4 4.6 7.0 6.93 8.1 IF false
ONE CYCLE AND
WAIT
WAIT (exe-
cution con-
dition)
805 1 12.6 12.6 13.7 16.7 28.6 34.0 WAIT condition sat-
isfied
3.9 3.9 4.1 6.3 5.6 6.9 WAIT condition not
satisfied
ONE CYCLE AND
WAIT
WAIT
(relay num-
ber)
805 2 12.0 12.0 13.4 16.5 27.2 30.0 WAIT condition sat-
isfied
6.1 6.1 6.5 9.6 10.0 11.4 WAIT condition not
satisfied
ONE CYCLE AND
WAIT (NOT)
WAIT NOT
(relay num-
ber)
805 2 12.2 12.2 13.8 17.0 27.8 30.6 WAIT condition sat-
isfied
6.4 6.4 6.9 10.1 10.5 11.8 WAIT condition not
satisfied
COUNTER WAIT CNTW 814 4 17.9 17.9 22.6 27.4 41.0 43.5 First execution
19.1 19.1 23.9 28.7 42.9 45.7 Normal execution
CNTWX 818 4 17.9 17.9 22.6 27.4 41.0 43.5 First execution
19.1 19.1 23.9 28.7 42.9 45.7 Normal execution
HIGH-SPEED
TIMER WAIT
TMHW 815 3 25.8 25.8 27.9 34.1 47.9 53.7 First execution
20.6 20.6 22.7 28.9 40.9 46.2 Normal execution
TMHWX 817 3 25.8 25.8 27.9 34.1 47.9 53.7 First execution
20.6 20.6 22.7 28.9 40.9 46.2 Normal execution
Loop Control LOOP 809 1 7.9 7.9 9.1 12.3 15.6 17.6 ---
Loop Control LEND
(execution
condition)
810 1 7.7 7.7 8.4 10.9 13.5 15.5 LEND condition
satisfied
6.8 6.8 8.0 9.8 17.5 19.8 LEND condition not
satisfied
Loop Control LEND
(relay num-
ber)
810 2 9.9 9.9 10.7 14.4 17.5 19.9 LEND condition
satisfied
8.9 8.9 10.3 13.0 21.6 24.5 LEND condition not
satisfied
Loop Control LEND NOT
(relay num-
ber)
810 2 10.2 10.2 11.2 14.8 21.9 24.9 LEND condition
satisfied
9.3 9.3 10.8 13.5 17.8 20.4 LEND condition not
satisfied
TIMER WAIT TIMW 813 3 22.3 22.3 25.2 33.1 47.4 52.0 Default setting
24.9 24.9 27.8 35.7 46.2 53.4 Normal execution
TIMWX 816 3 22.3 22.3 25.2 33.1 47.4 52.0 Default setting
24.9 24.9 27.8 35.7 46.2 53.4 Normal execution
Instruction Mnemonic Code Length
(steps)
(See
note.)
ON execution time (
µs) Conditions
CPU6@H-R CPU6@HCPU4@HCPU4@ CJ1M
excluding
CPU11/21
CJ1M
CPU11/21
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