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Shift Instructions Section 5-16
the reset bit is OFF and as long as bit 14 is ON. If SFTR(84) is executed with
an OFF execution condition or if SFTR(84) is executed with bit 14 OFF, the
shift register will remain unchanged. If SFTR(84) is executed with an ON exe-
cution condition and the reset bit (bit 15) is OFF, the entire shift register and
CY will be set to zero.
Flags ER: St and E are not in the same data area or ST is greater than E.
Indirectly addressed DM word is non-existent. (Content of *DM word
is not BCD, or the DM area boundary has been exceeded.)
CY: Receives the status of bit 00 of St or bit 15 of E, depending on the
shift direction.
Example In the following example, IR 00000, IR 00001, IR 00002, and IR 00003 are
used to control the bits of C used in @SFTR(84). The shift register is in DM
0010, and it is controlled through IR 00004.
5-16-10ASYNCHRONOUS SHIFT REGISTER – ASFT(17)
Note ASFT(17) is an expansion instruction for the SRM1. The function code 17 is
the factory setting and can be changed for the SRM1 if desired.
Limitations St and E must be in the same data area, and E must be greater than or equal
to St.
DM 6144 to DM 6655 cannot be used for St or E.
00000 LD 00000
00001 OUT 03512
00002 LD 00001
00003 OUT 03513
00004 LD 00002
00005 OUT 03514
00006 LD 00003
00007 OUT 03515
00008 LD 00004
00009 @SFT(10)
035
DM 0010
DM 0010
Address Instruction Operands
00000
00001
00002
00003
00004
03512
03513
03514
03515
Direction
Status to input
Shift pulse
Reset
@SFTR(84)
035
DM 0010
DM 0010
ASFT(17)
C
St
E
Ladder Symbols
@ASFT(17)
C
St
E
C: Control word
IR, SR, AR, DM, HR, LR, #
St: Starting word
IR, SR, AR, DM, HR, LR
E: End word
IR, SR, AR, DM, HR, LR
Operand Data Areas