63
CQM1 Interrupt Functions Section 1-5
Absolute High-speed Counter Settings (DM 6643 and DM 6644)
DM 6643 contains the settings for absolute high-speed counter 1, and DM
6644 contains the settings for absolute high-speed counter 2. These words
determine the count modes and resolution settings.
Origin Compensation It is possible to compensate for an offset between an absolute rotary
encoder’s origin and the actual origin. This adjustment can be made sepa-
rately for ports 1 and 2.
Follow the procedure below to set origin compensation. After origin compen-
sation has been set, the data from the encoder will be adjusted before being
output as the PV.
1,2,3... 1. Set the absolute rotary encoder to the desired origin location.
2. Make sure that pin 1 of the CPU Unit’s DIP switch is OFF (enabling Periph-
eral Devices to overwrite DM 6614 through DM 6655) and switch the PC to
PROGRAM mode.
3. Set the resolution setting in DM 6643 or DM 6644.
4. Make sure that a fatal error or FALS 9C error have not occurred.
5. Read the high-speed counter’s PV from IR 232 and IR 233 (port 1) or IR
234 and IR 235 (port 2) to determine the PV before origin compensation.
6. Turn ON the Port 1 Origin Compensation flag (SR 25201) or Port 2 Origin
Compensation flag (SR 25202) from a Peripheral Device.
The compensation value will be written to DM 6611 (port 1) or DM 6612
(port 2) and the Origin Compensation flag will be turned OFF automatical-
ly. The compensation value will be recorded in BCD between 0000 and
4095 whether the counter is set to BCD mode or 360
° mode.
7. Read the high-speed counter’s PV to determine the PV after origin com-
pensation. The PV should be 0000 after origin compensation.
The compensation value will be valid until it is changed again by the proce-
dure above.
Programming Use the following steps to program absolute high-speed counters 1 and 2.
Absolute high-speed counters 1 and 2 begin counting when the proper PC
Setup settings are made, but comparisons will not be made with the compari-
son table and interrupts will not be generated unless the CTBL(63) instruction
is executed.
The present value of absolute high-speed counter 1 is maintained in IR 232
and IR 233 and the present value of absolute high-speed counter 2 is main-
tained in IR 234 and IR 235.
15 0
DM6643/DM 6644
Bit
Count mode:
00: BCD mode
01: 360˚ mode
Resolution setting:
00: 8-bit
01: 10-bit
02: 12-bit
Defaults: BCD mode, 8-bit resolution