Renesas RL78/G13 User Manual

RL78/G13 CHAPTER 11 A/D CONVERTER
R01UH0146EJ0100 Rev.1.00 484
Sep 22, 2011
Table 11-3. A/D Conversion Time Selection (1/8)
(1) 3.6 V ≤ V
DD ≤ 5.5 V
When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode)
A/D Converter Mode Register 0 (ADM0) Conversion Time Selection
FR2 FR1 FR0 LV1 LV0
Mode
f
CLK =
1 MHz
fCLK =
2 MHz
fCLK =
4 MHz
fCLK =
8 MHz
fCLK = 16
MHz
fCLK = 32
MHz
Conversion
Clock (f
AD)
0 0 0
Setting
prohibited
38
μ s fCLK/64
0 0 1
Setting
prohibited
38 μ s 19 μ s fCLK/32
0 1 0
Setting
prohibited
38 μ s 19 μ s 9.5 μ s fCLK/16
0 1 1 38 μ s 19 μ s 9.5 μ s 4.75 μ s fCLK/8
1 0 0 28.5 μ s 14.25 μ s 7.125 μ s 3.5625 μ s fCLK/6
1 0 1
Setting
prohibited
23.75 μ s 11.875 μ s 5.938 μ s 2.9688 μ s fCLK/5
1 1 0
Setting
prohibited
38 μ s 19 μ s 9.5 μ s 4.75 μ s 2.375 μ s fCLK/4
1 1 1
0 0 Normal 1
38 μ s 19 μ s 9.5 μ s 4.75 μ s 2.375 μ s
Setting
prohibited
fCLK/2
0 0 0
Setting
prohibited
34 μ s fCLK/64
0 0 1
Setting
prohibited
34 μ s 17 μ s fCLK/32
0 1 0
Setting
prohibited
34 μ s 17 μ s 8.5 μ s fCLK/16
0 1 1 34 μ s 17 μ s 8.5 μ s 4.25 μ s fCLK/8
1 0 0 25.5 μ s 12.75 μ s 6.375 μ s 3.1875 μ s fCLK/6
1 0 1
Setting
prohibited
21.25 μ s 10.625 μ s 5.3125 μ s 2.6563 μ s fCLK/5
1 1 0
Setting
prohibited
34 μ s 17 μ s 8.5 μ s 4.25 μ s 2.125 μ s fCLK/4
1 1 1
0 1 Normal 2
34 μ s 17 μ s 8.5 μ s 4.25 μ s 2.125 μ s
Setting
prohibited
fCLK/2
× × ×
1 0
Low-
voltage 1
Setting prohibited
−
× × ×
1 1
Low-
voltage 2
Setting prohibited
−
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include clock frequency errors. Select conversion time, taking
clock frequency errors into consideration.
Remark f
CLK: CPU/peripheral hardware clock frequency

Renesas RL78/G13 Specifications

General

Brand	Renesas
Model	RL78/G13
Category	Computer Hardware
Language	English