Siemens D7-SYS - Page 468

Closed-loop thyristor current control
5-28 System- and communication configuring D7-SYS - SIMADYN D
Edition 06.2002
YW1→YF1 Fault message → remedy Source
Bit 1 Synchronizing voltage not present / failed
→ check the synchronizing voltage connection (hardware)
PA6
Bit 2 ∅
Erroneous synchronizing voltage
Frequency step > 10% / periods
→ check the synchronizing voltage (hardware)
PA6
Bit 3 ∅
Zero crossovers UL1-2 missing (Sitor)
only, if the signal was present once.
→ check the line supply connection and initialization connection PA6.INV
PA6
Bit 4 ∅
Zero crossovers UL1-3 missing (Sitor)
only, if the signal was present once.
→ check the line supply connection and initialization connection PA6.INV
PA6
Bit 5 ∅
Rotating field error = no clockwise rotating field of Vsyn.,
or both zero crossovers missing.
(dependent on the mode: INV)
→ check the line supply connection and initialization connection PA6.INV
PA6
Bit 6 ∅
Undervoltage (Sitor).
(dependent on the mode: UNM)
→ check the line supply values and connector SOL.UNM
SOL
Bit 7 ∅
Logical 0
Bit 8
Pulse inhibit, software (.IPL = 1) + hardware command: Total pulse inhibit SOL
Bit 9
Fault, external 1 (SOL.IF1= 1) SOL
Bit 10 ∅
Fuse monitoring (Sitor)
→ check for fuse failure
SOL
Bit 11 ∅
Temperature monitoring (Sitor)
→ check for overtemperature
SOL
Bit 12
Fault, external 2 (SOL.IF2 = 1) SOL
Bit 13
External pulse inhibit for voltage missing at the input
+ hardware command: Total pulse inhibit
→ ITDC-X5:10 > 15 V
=
ˆ
enable the pulses
SOL
Bit 14
Excitation current fault
(optional for SITOR set 6QG3x with excitation option)
Cause: FCS.FC > 5% and field current actual value < 3% FCS.ARC
→ check the field control/connection
FCS
Bit 15 Hardware Watchdog ITDC + hardware command: Total pulse inhibit
Causes: Defective module,
→ replace the module
Task overflow in the PMx
→ change the application software
SOL
Bit 16 Hardware command: Total pulse inhibit (ITDC-X5:15)
→ remove the fault statuses
SOL
Table 5-5 Fault list SOL.YW1 .YF1
Significance of the
fault bits YW1, with
HM1 → YF1