Product Overview
1-17
High Speed Counter Encoder Module User Manual
1.8 Counting with 16-Bit Counters
General
information for all 16-bit counter modes is presented in following
paragraphs. Figure 1-12 shows that incrementing or decrementing the
count value occurs on the rising edge of the input clock signal.
A valid clock is a high-to-low-to-high transition; or from the input viewpoint,
the clock input goes from On-to-Off-to-On.
A trigger is an On–to-Off pulse edge. The trigger or gate, followed by a valid
clock pulse, sets the timer for proper operation.
A gate pauses the counter on an Off-to-On edge, reloads the preset value,
and starts counting on the On-to-Off edge.
When the corresponding Reset Counter flag, WY19.03, .04, .07, or .08 for
counter 2, 3, 5, or 6 is set and then cleared; the preset value, read during
Program mode or Preset Update (Run mode), is reloaded into the counter
.
The external trigger/gate signal and the Reset Counter flag, are Or
’d into
the count trigger/gate control. Only one signal, the external trigger or the
Reset Counter flag, can change state, the other must be 0 (Off).
The 16-bit counter outputs 8, 7, 4, or 3 are OR’ed with the corresponding
Force Output On bit WY19.09, .10, .13, or .14. If the corresponding Force
Output On bit is 1, the output is forced On and overrides the counter
output.
Clock
Trigger
Rising
clock edge
loads preset into counter
.
Figure 1-12 Clock
and T
rigger for 16-Bit Counters
16–Bit Counter
General
Description
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