Product Overview
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High Speed Counter Encoder Module User Manual
Counting with 16-Bit Counters (continued)
Divide-by-N
counting generates an output that is On for one clock period
every count cycle. The length of the count cycle is the preset number of
clocks. The counter counts down from the preset value to 1.
The first valid clock pulse, after the gate, loads the preset value (3) and
starts decrementing the counter
. When the count value is 1, the output
turns On. At the next clock the count would be zero, however, the counter
automatically reloads the preset and turns the output Off.
Y
ou can use a gate signal to stop the counting and reload the preset value. A
gate can be an external signal or the PLC can set the Reset Counter flags
(WY19.03, .04, .07, .08). When the gate goes On (high), the counter pauses,
and the output is turned Off. When the gate turns Off, or the Reset Counter
flag is cleared, the preset is loaded into the counter and counting resumes
on the next valid clock pulse.
A typical, Divide-by-N counting waveform is presented in Figure 1-14. The
waveforms show that the output is initially Off after the gate. The gate
input On enables the counter; Off inhibits the counter
. When the counter
counts the preset value (3) down to 1, the output goes On for one clock
period then goes Off. The preset value is reloaded and the cycle continues. If
the gate goes Off when the output is Off, the output is set On immediately
.
In this example, the preset value is 3.
Pulse
Input
Starts Of
f
Gate, Reset, or
Programming
Output
Starts On
20 3 2 1 3 2 1 3 3 320 3 2 1 3 2
20 3 2 1 3 2 1 3 3 319 3 2 1 3 2
Figure 1-14 Divide-by-N
Mode
Divide-by-N
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