VIPA CPU 21 Series User Manual

Chapter 7 Deployment of the CPU 21xDP Manual VIPA CPU 21x
7-4 HB103E - Rev. 05/45
The data exchange between the DP master and the DP slave is performed
in a cycle using send and receive buffers.
DP-Master
Input
Output
CPU 21x DP with I/O-Modules
I/O ModulesCommunications
Processor
buffer receive
Profibus DP
V-Bus
buffer send
V-Bus-ZyklusDP-Zyklus
PI
PO
PI: Process image of the inputs
PO: Process image of the outputs
In one V-bus cycle (V-bus = VIPA-backplane bus) all input data of the
single modules are collected in the PE and all output data from the PO are
transferred to the output modules. After the data exchange is completed,
the PI is transferred to the sending buffer (buffer send) and the content of
the input buffer (buffer receive) is transferred to PO.
In one Profibus cycle the master contacts all its slaves with a data ex-
change. There the memory areas assigned to the Profibus are written resp.
read.
Afterwards the DP master transmits data of the input area to the receive
buffer of the communication processor and the data of the send buffer is
transferred into the Profibus output area.
The DP master to DP slave data exchange on the bus is repeated cyclically
and does not depend on the V-bus cycle.
The principle of
data transfer
operations
V-bus cycle
DP cycle

VIPA CPU 21 Series Specifications

General

Brand	VIPA
Model	CPU 21 Series
Category	Control Unit
Language	English