Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 184
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
C_M_AXI_IC_ARUSER_WIDTH Instruction cache AXI
user width
5 5
integer
C_M_AXI_IC_WUSER_WIDTH Instruction cache AXI
user width
1 1
integer
C_M_AXI_IC_RUSER_WIDTH Instruction cache AXI
user width
1 1
integer
C_M_AXI_IC_BUSER_WIDTH Instruction cache AXI
user width
1 1
integer
C_M_AXI_IC_USER_VALUE Instruction cache AXI
user value
0-31 31
integer
C_STREAM_INTERCONNECT Select AXI4-Stream
interconnect
0,1 0
integer
C_Mn_AXIS_PROTOCOL AXI4-Stream protocol
GENERIC GENERIC
string
C_Sn_AXIS_PROTOCOL AXI4-Stream protocol
GENERIC GENERIC
string
C_Mn_AXIS_DATA_WIDTH AXI4-Stream master
data width
32 32 NA
integer
C_Sn_AXIS_DATA_WIDTH AXI4-Stream slave data
width
32 32 NA
integer
C_NUM_SYNC_FF_CLK Reset and Wakeup[0:1]
synchronization stages
0- 2
integer
C_NUM_SYNC_FF_CLK_IRQ Interrupt input signal
synchronization stages
0- 1
integer
C_NUM_SYNC_FF_CLK_DEBUG Dbg_ serial signal
synchronization stages
0- 2
integer
C_NUM_SYNC_FF_DBG_CLK Internal synchronization
stages to Dbg_Clk
0- 1
integer
C_NUM_SYNC_FF_DBG_TRACE_CLK Internal synchronization
stages to Dbg_Trace_Clk
0- 1
integer
1. The 7 least significant bits must all be 0.
2. Not all sizes are permitted in all architectures. The cache uses 0 - 32 RAMB primitives (0 if cache size is less than 2048).
3. Not available when
C_AREA_OPTIMIZED is set to 1 (Area).
1.
Table 3-19: Configuration Parameters (Cont’d)
Parameter Name Feature/Description
Allowable
Values
Default
Value
Tool
Assigned
VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module