Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 183
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
C_M_AXI_DC_PROTOCOL Data cache AXI protocol AXI4 AXI4 string
C_M_AXI_DC_AWUSER_WIDTH Data cache AXI user
width
5 5
integer
C_M_AXI_DC_ARUSER_WIDTH Data cache AXI user
width
5 5
integer
C_M_AXI_DC_WUSER_WIDTH Data cache AXI user
width
1 1
integer
C_M_AXI_DC_RUSER_WIDTH Data cache AXI user
width
1 1
integer
C_M_AXI_DC_BUSER_WIDTH Data cache AXI user
width
1 1
integer
C_M_AXI_DC_
EXCLUSIVE_ACCESS
Data cache AXI exclusive
access support
0,1 0
integer
C_M_AXI_DC_USER_VALUE Data cache AXI user
value
0-31 31
integer
C_M_AXI_IC_
THREAD_ID_WIDTH
Instruction cache AXI ID
width
1 1
integer
C_M_AXI_IC_DATA_WIDTH Instruction cache AXI
data width
32, 64, 128,
256, 512
32
integer
C_M_AXI_IC_ADDR_WIDTH Instruction cache AXI
address width
32-64 32 yes
integer
C_M_AXI_IC_
SUPPORTS_THREADS
Instruction cache AXI
uses threads
0 0
integer
C_M_AXI_IC_SUPPORTS_READ Instruction cache AXI
support for read
accesses
1 1
integer
C_M_AXI_IC_SUPPORTS_WRITE Instruction cache AXI
support for write
accesses
0 0
integer
C_M_AXI_IC_SUPPORTS_
NARROW_BURST
Instruction cache AXI
narrow burst support
0 0
integer
C_M_AXI_IC_SUPPORTS_
USER_SIGNALS
Instruction cache AXI
user signal support
1 1
integer
C_M_AXI_IC_PROTOCOL Instruction cache AXI
protocol
AXI4 AXI4
string
C_M_AXI_IC_AWUSER_WIDTH Instruction cache AXI
user width
5 5
integer
Table 3-19: Configuration Parameters (Cont’d)
Parameter Name Feature/Description
Allowable
Values
Default
Value
Tool
Assigned
VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module