Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 182
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
C_M_AXI_DP_PROTOCOL Data side AXI protocol AXI4,
AXI4LITE
AXI4
LITE
yes
string
C_M_AXI_DP_
EXCLUSIVE_ACCESS
Data side AXI exclusive
access support
0,1 0
integer
C_M_AXI_IP_
THREAD_ID_WIDTH
Instruction side AXI
thread ID width
1 1
integer
C_M_AXI_IP_DATA_WIDTH Instruction side AXI data
width
32 32
integer
C_M_AXI_IP_ADDR_WIDTH Instruction side AXI
address width
32-64 32 yes
integer
C_M_AXI_IP_
SUPPORTS_THREADS
Instruction side AXI uses
threads
0 0
integer
C_M_AXI_IP_SUPPORTS_READ Instruction side AXI
support for read
accesses
1 1
integer
C_M_AXI_IP_SUPPORTS_WRITE Instruction side AXI
support for write
accesses
0 0
integer
C_M_AXI_IP_SUPPORTS_
NARROW_BURST
Instruction side AXI
narrow burst support
0 0
integer
C_M_AXI_IP_PROTOCOL Instruction side AXI
protocol
AXI4LITE
AXI4
LITE
string
C_M_AXI_DC_
THREAD_ID_WIDTH
Data cache AXI ID width
1 1
integer
C_M_AXI_DC_DATA_WIDTH Data cache AXI data
width
32, 64, 128,
256, 512
32
integer
C_M_AXI_DC_ADDR_WIDTH Data cache AXI address
width
32-64 32 yes
integer
C_M_AXI_DC_
SUPPORTS_THREADS
Data cache AXI uses
threads
0 0
integer
C_M_AXI_DC_SUPPORTS_READ Data cache AXI support
for read accesses
1 1
integer
C_M_AXI_DC_SUPPORTS_WRITE Data cache AXI support
for write accesses
1 1
integer
C_M_AXI_DC_SUPPORTS_
NARROW_BURST
Data cache AXI narrow
burst support
0 0
integer
C_M_AXI_DC_SUPPORTS_
USER_SIGNALS
Data cache AXI user
signal support
1 1
integer
Table 3-19: Configuration Parameters (Cont’d)
Parameter Name Feature/Description
Allowable
Values
Default
Value
Tool
Assigned
VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module