Xilinx MicroBlaze - Page 180

MicroBlaze Processor Reference Guide 181
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
C_USE_INTERRUPT Enable interrupt
handling
0 = No interrupt
1 = Standard interrupt
2 = Low-latency
interrupt
0, 1, 2 1 yes integer
C_USE_EXT_BRK Enable external break
handling
0,1 0
yes
integer
C_USE_EXT_NM_BRK Enable external non-
maskable break
handling
0,1 0 yes integer
C_USE_NON_SECURE Use corresponding non-
secure input
0-15 0 yes integer
C_USE_BRANCH_TARGET_CACHE
3
Enable Branch Target
Cache
0,1 0 integer
C_BRANCH_TARGET_CACHE_SIZE
3
Branch Target Cache
size:
0 = Default
1 = 8 entries
2 = 16 entries
3 = 32 entries
4 = 64 entries
5 = 512 entries
6 = 1024 entries
7 = 2048 entries
0-7 0 integer
C_M_AXI_DP_
THREAD_ID_WIDTH
Data side AXI thread ID
width
1 1
integer
C_M_AXI_DP_DATA_WIDTH Data side AXI data width 32 32 integer
C_M_AXI_DP_ADDR_WIDTH Data side AXI address
width
32-64 32 yes
integer
C_M_AXI_DP_
SUPPORTS_THREADS
Data side AXI uses
threads
0 0
integer
C_M_AXI_DP_SUPPORTS_READ Data side AXI support
for read accesses
1 1
integer
C_M_AXI_DP_SUPPORTS_WRITE Data side AXI support
for write accesses
1 1
integer
C_M_AXI_DP_SUPPORTS_
NARROW_BURST
Data side AXI narrow
burst support
0 0
integer
Table 3-19: Configuration Parameters (Cont’d)
Parameter Name Feature/Description
Allowable
Values
Default
Value
Tool
Assigned
VHDL Type
Send Feedback