MicroBlaze Processor Reference Guide 220
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
brki
Break Immediate
brki
rD, IMM
1 0 1 1 1 0 rD 0 1 1 0 0 IMM
0 6 11 16
31
Description
Branch and link to the instruction located at address value in IMM, sign-extended to 32 bits. The
current value of PC will be stored in rD. The BIP flag in the MSR will be set, except in case of a Software
Break, and the reservation bit will be cleared.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged,
except as a special case when “brki rD, C_BASE_VECTORS+0x8” or “brki rD,
C_BASE_VECTORS+0x18” is used to perform a Software Break. This means that, apart from the
special case, if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction
exception occurs.
As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and “brki rD,
C_BASE_VECTORS+0x8” or “brki rD, C_BASE_VECTORS+0x18” is used to perform a Software
Break, the Machine Status Register bits User Mode and Virtual Mode are cleared.
Pseudocode
if MSR[UM] and IMM ≠ C_BASE_VECTORS+0x8 and IMM ≠ C_BASE_VECTORS+0x18 then
ESR[EC] ← 00111
else
(rD)
← PC
PC ← sext(IMM)
if IMM
≠ 0x18 then
MSR[BIP] ← 1
Reservation ← 0
if IMM = C_BASE_VECTORS+0x8 or IMM = C_BASE_VECTORS+0x18 then
MSR[UMS] ← MSR[UM]
MSR[UM] ← 0
MSR[VMS]
← MSR[VM]
MSR[VM] ← 0
Registers Altered
• rD, unless an exception is generated, in which case the register is unchanged
•PC
• MSR[BIP], MSR[UM], MSR[VM]
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 3 cycles
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