MicroBlaze Processor Reference Guide 252
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
Registers Altered
• rD and MSR[C], unless an exception is generated, in which case they are unchanged
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
Latency
• 1 cycle with C_AREA_OPTIMIZED=0 or 2
• 2 cycles with
C_AREA_OPTIMIZED=1
Notes
This instruction is used together with SWX to implement exclusive access, such as semaphores and
spinlocks.
The carry flag (MSR[C]) might not be set immediately (dependent on pipeline stall behavior). The LWX
instruction should not be immediately followed by an MSRCLR, MSRSET, MTS, or SRC instruction, to
ensure the correct value of the carry flag is obtained.
mbar
Memory Barrier
mbar
IMM
Memory Barrier
1 0 1 1 1 0 IMM 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
0 6 11 16
31
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