Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 254
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
mfs
Move From Special Purpose Register
mfs
rD, rS
mfse
rD, rS
1 0 0 1 0 1 rD 0 E 0 0 0 1 0 rS
0 6 11 16 18
31
Description
Copies the contents of the special purpose register rS into register rD. The special purpose registers
TLBLO and TLBHI are used to copy the contents of the Unified TLB entry indexed by TLBX.
If the E bit is set, the extended part of the special register is moved. The EAR, PVR[8] and PVR[9}
registers have extended parts when extended addressing is enabled (C_ADDR_SIZE > 32), and the
TLBLO, PVR[6] and PVR[7] registers have extended parts when Physical Address Extension (PAE) is
enabled.
Pseudocode
if E = 1 then
switch (rS):
case 0x0003 : (rD) ← EAR[0:C_ADDR_SIZE-32-1]
case 0x1003 : (rD)
← TLBLO[0:C_ADDR_SIZE-32-1]
case 0x2006 : (rD) ← PVR6[0:C_ADDR_SIZE-32-1]
case 0x2007 : (rD) ← PVR7[0:C_ADDR_SIZE-32-1]
case 0x2008 : (rD)
← PVR8[0:C_ADDR_SIZE-32-1]
case 0x2009 : (rD) ← PVR9[0:C_ADDR_SIZE-32-1]
default : (rD) ← Undefined
else
switch (rS):
case 0x0000 : (rD)
← PC
case 0x0001 : (rD)
← MSR
case 0x0003 : (rD) ← EAR[C_ADDR_SIZE-32:C_ADDR_SIZE-1]
case 0x0005 : (rD) ← ESR
case 0x0007 : (rD)
← FSR
case 0x000B : (rD) ← BTR
case 0x000D : (rD) ← EDR
case 0x0800 : (rD)
← SLR
case 0x0802 : (rD) ← SHR
case 0x1000 : (rD) ← PID
case 0x1001 : (rD)
← ZPR
case 0x1002 : (rD) ← TLBX
case 0x1003 : (rD) ← TLBLO[C_ADDR_SIZE-32:C_ADDR_SIZE-1]
case 0x1004 : (rD)
← TLBHI
case 0x200x : (rD) ← PVRx[C_ADDR_SIZE-32:C_ADDR_SIZE-1] (where x = 0 to 12)
default : (rD) ← Undefined
Registers Altered
•rD
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module