MicroBlaze Processor Reference Guide 256
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
msrclr
Read MSR and clear bits in MSR
msrclr
rD, Imm
1 0 0 1 0 1 rD 1 0 0 0 1 0 Imm15
0 6 11 17
31
Description
Copies the contents of the special purpose register MSR into register rD. Bit positions in the IMM
value that are 1 are cleared in the MSR. Bit positions that are 0 in the IMM value are left untouched.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged for all
IMM values except those only affecting C. This means that if the instruction is attempted in User Mode
(MSR[UM] = 1) in this case a Privileged Instruction exception occurs.
Pseudocode
if MSR[UM] = 1 and IMM ≠ 0x4 then
ESR[EC] ← 00111
else
(rD)
← (MSR)
(MSR) ← (MSR) ∧ (IMM))
Registers Altered
•rD
•MSR
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 1 cycle
Notes
MSRCLR will affect the Carry bit immediately while the remaining bits will take effect one cycle after
the instruction has been executed. When clearing the IE bit, it is guaranteed that the processor will not
react to any interrupt for the subsequent instructions.
The value read from MSR might not include effects of the immediately preceding instruction
(dependent on pipeline stall behavior). An instruction that does not affect MSR must precede the
MSRCLR instruction to guarantee correct MSR value. This applies to both the value copied to register
rD and the changed MSR value itself.
The immediate values has to be less than 215 when C_USE_MMU >= 1 (User Mode), and less than 214
otherwise. Only bits 17 to 31 of the MSR can be cleared when C_USE_MMU >= 1 (User Mode), and.bits
18 to 31 otherwise.
This instruction is only available when the parameter C_USE_MSR_INSTR is set to 1.
When clearing MSR[VM] the instruction must always be followed by a synchronizing branch
instruction, for example BRI 4.
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