MicroBlaze Processor Reference Guide 258
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
mts
Move To Special Purpose Register
mts rS, rA
mtse rS, rA
1 0 0 1 0 1 0 E 0 0 0 rA 1 1 rS
0 6 11 16 18
31
Description
Copies the contents of register rD into the special purpose register rS. The special purpose registers
TLBLO and TLBHI are used to copy to the Unified TLB entry indexed by TLBX.
If the E bit is set, the extended part of the special register is moved. The TLBLO register has an
extended part when the Physical Address Extension (PAE) is enabled.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This
means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction
exception occurs.
With low-latency interrupt mode (C_USE_INTERRUPT = 2), the Interrupt_Ack output port is set to 11
if the MSR{IE] bit is set by executing this instruction.
Pseudocode
if MSR[UM] = 1 then
ESR[EC] ← 00111
else
if E = 1 then
if (rS) = 0x1003 then
TLBLO[0:C_ADDR_SIZE-32-1]
← (rA)
else
switch (rS)
case 0x0001 : MSR ← (rA)
case 0x0007 : FSR ← (rA)
case 0x0800 : SLR ← (rA)
case 0x0802 : SHR ← (rA)
case 0x1000 : PID ← (rA)
case 0x1001 : ZPR ← (rA)
case 0x1002 : TLBX ← (rA)
case 0x1003 : TLBLO[C_ADDR_SIZE-32:C_ADDR_SIZE-1] ← (rA)
case 0x1004 : TLBHI ← (rA)
case 0x1005 : TLBSX ← (rA)
if (rS) = 0x0001 and (rA) & 2
Interrupt_Ack ← 11
Registers Altered
•rS
• ESR[EC], in case a privileged instruction exception is generated
To Next Page
Loading...
