Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 27
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Table 2-9: Machine Status Register (MSR)
Bits Name Description Reset Value
0 CC Arithmetic Carry Copy
Copy of the Arithmetic Carry (bit 29). CC is always the same as bit C.
0
1:16 Reserved
17 VMS Virtual Protected Mode Save
Only available when configured with an MMU
(if C_USE_MMU > 1 and C_AREA_OPTIMIZED = 0 or 2)
Read/Write
0
18 VM Virtual Protected Mode
0 = MMU address translation and access protection disabled, with
C_USE_MMU = 3 (Virtual). Access protection disabled with
C_USE_MMU = 2 (Protection)
1 = MMU address translation and access protection enabled, with
C_USE_MMU = 3 (Virtual). Access protection enabled, with
C_USE_MMU = 2 (Protection).
Only available when configured with an MMU
(if C_USE_MMU > 1 and C_AREA_OPTIMIZED = 0 or 2)
Read/Write
0
19 UMS User Mode Save
Only available when configured with an MMU
(if C_USE_MMU > 0 and C_AREA_OPTIMIZED = 0 or 2)
Read/Write
0
20 UM User Mode
0 = Privileged Mode, all instructions are allowed
1 = User Mode, certain instructions are not allowed
Only available when configured with an MMU
(if C_USE_MMU > 0 and C_AREA_OPTIMIZED = 0 or 2)
Read/Write
0
21 PVR Processor Version Register exists
0 = No Processor Version Register
1 = Processor Version Register exists
Read only
Based on
parameter
C_PVR
22 EIP Exception In Progress
0 = No hardware exception in progress
1 = Hardware exception in progress
Only available if configured with exception support
(
C_*_EXCEPTION or C_USE_MMU > 0)
Read/Write
0
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module