Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 28
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
23 EE Exception Enable
0 = Hardware exceptions disabled
1
1 = Hardware exceptions enabled
Only available if configured with exception support
(
C_*_EXCEPTION or C_USE_MMU > 0)
Read/Write
0
24 DCE Data Cache Enable
0 = Data Cache disabled
1 = Data Cache enabled
Only available if configured to use data cache (C_USE_DCACHE = 1)
Read/Write
0
25 DZO Division by Zero or Division Overflow
2
0 = No division by zero or division overflow has occurred
1 = Division by zero or division overflow has occurred
Only available if configured to use hardware divider
(C_USE_DIV = 1)
Read/Write
0
26 ICE Instruction Cache Enable
0 = Instruction Cache disabled
1 = Instruction Cache enabled
Only available if configured to use instruction cache
(C_USE_ICACHE = 1)
Read/Write
0
27 FSL AXI4-Stream Error
0 = get or getd had no error
1 = get or getd control type mismatch
This bit is sticky, that is it is set by a get or getd instruction when a
control bit mismatch occurs. To clear it an MTS or MSRCLR instruction
must be used.
Only available if configured to use stream links (C_FSL_LINKS > 0)
Read/Write
0
28 BIP Break in Progress
0 = No Break in Progress
1 = Break in Progress
Break Sources can be software break instruction or hardware break
from
Ext_Brk or Ext_NM_Brk pin.
Read/Write
0
Table 2-9: Machine Status Register (MSR) (Cont’d)
Bits Name Description Reset Value
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module