Xilinx MicroBlaze - Page 284

MicroBlaze Processor Reference Guide 285
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
sh
Store Halfword
sh
rD, rA, rB
shr
rD, rA, rB
shea
rD, rA, rB
1 1 0 1 0 1 rD rA rB 0 R 0 EA 0 0 0 0 0 0 0
0 6 11 16 21
31
Description
Stores the contents of the least significant halfword of register rD, into the halfword aligned memory
location that results from adding the contents of registers rA and rB.
If the R bit is set, a halfword reversed memory location is used and the two bytes in the halfword are
reversed, storing data with the opposite endianness of the endianness defined by the E bit (if virtual
protected mode is enabled).
If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of adding
them.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-
access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.
An unaligned data access exception occurs if the least significant bit in the address is not zero.
A privileged instruction error occurs if the EA bit is set, Physical Address Extension (PAE) is enabled,
and the instruction is not explicitly allowed.
Pseudocode
if EA = 1 then
Addr ← (rA) & (rB)
else
Addr
← (rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC]← 10010;ESR[S]← 1
MSR[UMS]
← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[VM] = 1 then
ESR[EC] ← 10000;ESR[S]← 1; ESR[DIZ] ← No-access-allowed
MSR[UMS]
← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Addr[31] ≠ 0 then
ESR[EC] ← 00001; ESR[W] ← 0; ESR[S] ← 1; ESR[Rx] ← rD
else
Mem(Addr)
← (rD)[16:31]
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