MicroBlaze Processor Reference Guide 289
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
src
Shift Right with Carry
src
rD, rA
1 0 0 1 0 0 rD rA 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 6 11 16
31
Description
Shifts the contents of register rA, one bit to the right, and places the result in rD. The Carry flag is
shifted in the shift chain and placed in the most significant bit of rD. The least significant bit coming
out of the shift chain is placed in the Carry flag.
Pseudocode
(rD)[0] ← MSR[C]
(rD)[1:31]
← (rA)[0:30]
MSR[C] ← (rA)[31]
Registers Altered
•rD
•MSR[C]
Latency
• 1 cycle
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