Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 299
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
Pseudocode
if MSR[UM] = 1 then
ESR[EC] ← 00111
else
if C_DCACHE_USE_WRITEBACK = 1 then
if T = 1 and EA = 1 then
address
← (rA) & (rB)
else
address ← (rA) + (rB)
else if E = 0 then
address
← (rA)
else
address
← (rA) + (rB)
if C_DCACHE_LINE_LEN = 4 then
cacheline_mask ← (1 << log2(C_DCACHE_BYTE_SIZE) - 4) - 1
cacheline
← (DCache Line)[(address >> 4) ∧ cacheline_mask]
cacheline_addr ← address & 0xfffffff0
if C_DCACHE_LINE_LEN = 8 then
cacheline_mask
← (1 << log2(C_DCACHE_BYTE_SIZE) - 5) - 1
cacheline ← (DCache Line)[(address >> 5) ∧ cacheline_mask]
cacheline_addr ← address & 0xffffffe0
if C_DCACHE_LINE_LEN = 16 then
cacheline_mask
← (1 << log2(C_DCACHE_BYTE_SIZE) - 6) - 1
cacheline ← (DCache Line)[(address >> 6) ∧ cacheline_mask]
cacheline_addr
← address & 0xffffffc0
if E = 0 and F = 1 and cacheline.Dirty then
for i = 0 .. C_DCACHE_LINE_LEN - 1 loop
if cacheline.Valid[i] then
Mem(cacheline_addr + i * 4)
← cacheline.Data[i]
if T = 0 then
cacheline.Tag
← 0
else if cacheline.Address = cacheline_addr then
cacheline.Tag ← 0
if E = 1 then
if F = 1 then
request external cache flush with address
else
request external cache invalidate with address
Registers Altered
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 2 cycles for wdc.clear
• 2 cycles for wdc with
C_AREA_OPTIMIZED=0 or 2
• 3 cycles for wdc with
C_AREA_OPTIMIZED=0
• 2 + N cycles for wdc.flush, where N is the number of clock cycles required to flush the
cache line to memory when necessary
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module