Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 298
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
wdc
Write to Data Cache
wdc
rA,rB
wdc.flush
rA,rB
wdc.clear
rA,rB
wdc.clear.ea
rA,rB
wdc.ext.flush
rA,rB
wdc.ext.clear
rA,rB
1 0 0 1 0 0 0 0 0 0 0 rA rB E 0 0 EA 1 1 F 0 1 T 0
0 6 11 16 21
31
Description
Write into the data cache tag to invalidate or flush a cache line. The mnemonic wdc.flush is used to set
the F bit, wdc.clear is used to set the T bit, wdc.clear.ea is used to set the T and EA bits, wdc.ext.flush
is used to set the E, F and T bits, and wdc.ext.clear is used to set the E and T bits.
When C_DCACHE_USE_WRITEBACK is set to 1:
• If the F bits is set, the instruction will flush and invalidate the cache line.
• Otherwise, the instruction will only invalidate the cache line and discard any data that has not
been written to memory.
• If the T bit is set, only a cache line with a matching address is invalidated:
°
If the EA bit is set register rA concatenated with rB is the extended address of the affected
cache line.
°
Otherwise, register rA added with rB is the address of the affected cache line.
°
The EA bit is only taken into account when the parameter C_ADDR_SIZE > 32.
• The E bit is not taken into account.
• The F and T bits cannot be used at the same time.
When C_DCACHE_USE_WRITEBACK is cleared to 0:
• If the E bit is not set, the instruction will invalidate the cache line. Register rA contains the
address of the affected cache line, and the register rB value is not used.
• Otherwise, MicroBlaze will request that the matching address in an external cache should be
invalidated or flushed, depending on the value of the F bit, and invalidate the internal affected
cache line. Register rA added with rB is the address in the external cache, and of the affected
cache line.
• The E bit is only taken into account when the parameter C_INTERCONNECT is set to 3 (ACE).
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) the instruction is privileged. This
means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction
exception occurs.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module