Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 61
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
• Independent page sizes can be used for application modules, device drivers, system
service routines, and data. Independent page-size selection enables system software to
more efficiently use memory by reducing fragmentation (unused memory). For
example, a large data structure can be allocated to a 16 MB page and a small I/O
device-driver can be allocated to a 1 KB page.
• Page replacement can be tuned to minimize the occurrence of missing page
translations. As described in the following section, the most-frequently used page
translations are stored in the translation look-aside buffer (TLB).
Software is responsible for deciding which translations are stored in the TLB and which
translations are replaced when a new translation is required. The replacement strategy
can be tuned to avoid thrashing, whereby page-translation entries are constantly being
moved in and out of the TLB. The replacement strategy can also be tuned to prevent
replacement of critical-page translations, a process sometimes referred to as page
locking.
The unified 64-entry TLB, managed by software, caches a subset of instruction and data
page-translation entries accessible by the MMU. Software is responsible for reading entries
from the page-translation table in system memory and storing them in the TLB. The
following section describes the unified TLB in more detail. Internally, the MMU also contains
shadow TLBs for instructions and data, with sizes configurable by
C_MMU_ITLB_SIZE and
C_MMU_DTLB_SIZE respectively.
These shadow TLBs are managed entirely by the processor (transparent to software) and are
used to minimize access conflicts with the unified TLB.
Translation Look-Aside Buffer
The translation look-aside buffer (TLB) is used by the MicroBlaze MMU for address
translation when the processor is running in virtual mode, memory protection, and storage
control. Each entry within the TLB contains the information necessary to identify a virtual
page (PID and effective page number), specify its translation into a physical page,
determine the protection characteristics of the page, and specify the storage attributes
associated with the page.
The MicroBlaze TLB is physically implemented as three separate TLBs:
• Unified TLB: The UTLB contains 64 entries and is pseudo-associative. Instruction-page
and data-page translation can be stored in any UTLB entry. The initialization and
management of the UTLB is controlled completely by software.
• Instruction Shadow TLB: The ITLB contains instruction page-translation entries and is
fully associative. The page-translation entries stored in the ITLB represent the most-
recently accessed instruction-page translations from the UTLB. The ITLB is used to
minimize contention between instruction translation and UTLB-update operations. The
initialization and management of the ITLB is controlled completely by hardware and is
transparent to software.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module