Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 67
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Data-Storage Exception
When virtual mode is enabled, (MSR[VM]=1), a data-storage exception occurs when access
to a page is not permitted for any of the following reasons:
• From user mode:
-
The TLB entry specifies a zone field that prevents access to the page (ZPR[Zn]=00).
This applies to load and store instructions.
-
The TLB entry specifies a read-only page (TLBLO[WR]=0) that is not otherwise
overridden by the zone field (ZPR[Zn]‚ 11). This applies to store instructions.
• From privileged mode:
-
The TLB entry specifies a read-only page (TLBLO[WR]=0) that is not otherwise
overridden by the zone field (ZPR[Zn]‚ 10 and ZPR[Zn]‚ 11). This applies to store
instructions.
Instruction-Storage Exception
When virtual mode is enabled, (MSR[VM]=1), an instruction-storage exception occurs when
access to a page is not permitted for any of the following reasons:
• From user mode:
-
The TLB entry specifies a zone field that prevents access to the page (ZPR[Zn]=00).
-
The TLB entry specifies a non-executable page (TLBLO[EX]=0) that is not otherwise
overridden by the zone field (ZPR[Zn]‚ 11).
-
The TLB entry specifies a guarded-storage page (TLBLO[G]=1).
• From privileged mode:
-
The TLB entry specifies a non-executable page (TLBLO[EX]=0) that is not otherwise
overridden by the zone field (ZPR[Zn]‚ 10 and ZPR[Zn]‚ 11).
-
The TLB entry specifies a guarded-storage page (TLBLO[G]=1).
Data TLB-Miss Exception
When virtual mode is enabled (MSR[VM]=1) a data TLB-miss exception occurs if a valid,
matching TLB entry was not found in the TLB (shadow and UTLB). Any load or store
instruction can cause a data TLB-miss exception.
Instruction TLB-Miss Exception
When virtual mode is enabled (MSR[VM]=1) an instruction TLB-miss exception occurs if a
valid, matching TLB entry was not found in the TLB (shadow and UTLB). Any instruction
fetch can cause an instruction TLB-miss exception.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module