Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 66
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
The following figure diagrams the general process for examining a TLB entry.
The following sections describe the conditions under which exceptions occur due to TLB
access failures.
X-Ref Target - Figure 2-21
Figure 2-21: General Process for Examining a TLB Entry
Check TLB-Entry
Using Virtual Address
TLB HI[V]=1 TLB Entry Miss
No
TLBHI[TID]=0x00
Yes
Compare
TLBHI[TAG] with EA[EPN]
Using TLBHI[SIZE]
Compare
TLBHI[TID] with PID
TLB Entry Miss
No Match
Check Access Access Violation
Not allowed
Match (TLB Hit)
Allowed
Check for
Guarded Storage
Storage Violation
Guarded
Data Reference Instruction Fetch
Read TLBLO[RPN]
Using TLBHI[SIZE]
Extract Offset from EA
using TLBHI[SIZE]
Generate Physical Address from
TLBLO[RPN] and Offset
Yes No
Match
TLB Entry Miss
No Match
Not Guarded
X19758-091317
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module