Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 87
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
With the write-back protocol, a store to an address within the cacheable range always
updates the cached data. If the target address word is not in the cache (that is, the access
is a cache miss), and the location in the cache contains data that has not yet been written
to memory (the cache location is dirty), the old data is written over the data AXI4 interface
(
M_AXI_DC) to external memory before updating the cache with the new data. If only a
single word needs to be written, a single word write is used, otherwise a burst write is used.
For byte or halfword stores, in case of a cache miss, the address is first requested over the
data AXI4 interface, while a word store only updates the cache.
With the write-through protocol, a store to an address within the cacheable range
generates an equivalent byte, halfword, or word write over the data AXI4 interface to
external memory. The write also updates the cached data if the target address word is in the
cache (that is, the write is a cache hit). A write cache-miss does not load the associated
cache line into the cache.
Provided that the cache is enabled a load from an address within the cacheable range
triggers a check to determine if the requested data is currently cached. If it is (that is, on a
cache hit) the requested data is retrieved from the cache. If not (that is, on a cache miss) the
address is requested over the data AXI4 interface using a burst read, and the processor
pipeline stalls until the cache line associated to the requested address is returned from the
external memory controller.
The parameter C_DCACHE_DATA_WIDTH determines the bus data width, either 32 bits, an
entire cache line (128, 256 or 512 bits), or 512 bits.
When C_FAULT_TOLERANT is set to 1 and write-through protocol is used, a cache miss also
occurs if a parity error is detected in the tag or data block RAM.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module