Xilinx ZCU106 User Manual

ZCU106 Board User Guide 108
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-46: J5 HPC0 FMC Section G and H Connections to XCZU7EV U1
J5 Pin Schematic Net Name
I/O
Standard
U1
Pin
J5
Pin
Schematic Net Name
I/O
Standard
U1
Pin
G2 FMC_HPC0_CLK1_M2C_P LVDS G10 H1 NC
G3 FMC_HPC0_CLK1_M2C_N LVDS F10 H2 FMC_HPC0_PRSNT_M2C_B
(5)
G6 FMC_HPC0_LA00_CC_P LVDS F17 H4 FMC_HPC0_CLK0_M2C_P LVDS E15
G7 FMC_HPC0_LA00_CC_N LVDS F16 H5 FMC_HPC0_CLK0_M2C_N LVDS E14
G9 FMC_HPC0_LA03_P LVCMOS18 K19 H7 FMC_HPC0_LA02_P LVCMOS18 L20
G10 FMC_HPC0_LA03_N LVCMOS18 K18 H8 FMC_HPC0_LA02_N LVCMOS18 K20
G12 FMC_HPC0_LA08_P LVCMOS18 E18 H10 FMC_HPC0_LA04_P LVCMOS18 L17
G13 FMC_HPC0_LA08_N LVCMOS18 E17 H11 FMC_HPC0_LA04_N LVCMOS18 L16
G15 FMC_HPC0_LA12_P LVCMOS18 G18 H13 FMC_HPC0_LA07_P LVCMOS18 J16
G16 FMC_HPC0_LA12_N LVCMOS18 F18 H14 FMC_HPC0_LA07_N LVCMOS18 J15
G18 FMC_HPC0_LA16_P LVCMOS18 D17 H16 FMC_HPC0_LA11_P LVCMOS18 A13
G19 FMC_HPC0_LA16_N LVCMOS18 C17 H17 FMC_HPC0_LA11_N LVCMOS18 A12
G21 FMC_HPC0_LA20_P LVCMOS18 F12 H19 FMC_HPC0_LA15_P LVCMOS18 D16
G22 FMC_HPC0_LA20_N LVCMOS18 E12 H20 FMC_HPC0_LA15_N LVCMOS18 C16
G24 FMC_HPC0_LA22_P LVCMOS18 H13 H22 FMC_HPC0_LA19_P LVCMOS18 D12
G25 FMC_HPC0_LA22_N LVCMOS18 H12 H23 FMC_HPC0_LA19_N LVCMOS18 C11
G27 FMC_HPC0_LA25_P LVCMOS18 C7 H25 FMC_HPC0_LA21_P LVCMOS18 B10
G28 FMC_HPC0_LA25_N LVCMOS18 C6 H26 FMC_HPC0_LA21_N LVCMOS18 A10
G30 FMC_HPC0_LA29_P LVCMOS18 K10 H28 FMC_HPC0_LA24_P LVCMOS18 B6
G31 FMC_HPC0_LA29_N LVCMOS18 J10 H29 FMC_HPC0_LA24_N LVCMOS18 A6
G33 FMC_HPC0_LA31_P LVCMOS18 F7 H31 FMC_HPC0_LA28_P LVCMOS18 M13
G34 FMC_HPC0_LA31_N LVCMOS18 E7 H32 FMC_HPC0_LA28_N LVCMOS18 L13
G36 FMC_HPC0_LA33_P LVCMOS18 C9 H34 FMC_HPC0_LA30_P LVCMOS18 E9
G37 FMC_HPC0_LA33_N LVCMOS18 C8 H35 FMC_HPC0_LA30_N LVCMOS18 D9
G39 VADJ_FMC_BUS H37 FMC_HPC0_LA32_P LVCMOS18 F8
H38 FMC_HPC0_LA32_N LVCMOS18 E8
H40 VADJ_FMC_BUS
Notes:
1. Series capacitor coupled to FPGA U1 pin.
2. Connected to I2C switch U135 pins 4 and 5.
3. FPGA U1 JTAG TCK, TMS, TDO pins are buffered by U48 SN74AVC8T245.
4. J5 HPC0 TDO-TDI connections to U27 HPC0 FMC JTAG bypass switch (N.C. normally-closed/bypassing J5 until an FMC card
is plugged onto J5).
5. FMC_HPC0_PRSNT_M2C_B is the HPC FMC JTAG bypass switch U27.4 OE control signal, driven by I2C I/O expander U97.13.
6. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal.
7. U1 MGT (I/O standards do not apply).
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Xilinx ZCU106 Specifications

General

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English