Xilinx ZCU106

ZCU106 Board User Guide 132
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Appendix B: Master Constraints File Listing
#Other net PACKAGE_PIN W31 - DR4_SODIMM_DQS7_T Bank 504 - PS_DDR_DQS_P7
#Other net PACKAGE_PIN AG34 - DR4_SODIMM_DQS8_C Bank 504 - PS_DDR_DQS_N8
#Other net PACKAGE_PIN AG33 - DR4_SODIMM_DQS8_T Bank 504 - PS_DDR_DQS_P8
#DDR4 COMPONENT 64-BIT
set_propertyPACKAGE_PIN AK9 [get_ports "DDR4_A0"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A0"] ;
set_propertyPACKAGE_PIN AG11 [get_ports "DDR4_A1"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A1"] ;
set_propertyPACKAGE_PIN AJ10 [get_ports "DDR4_A2"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A2"] ;
set_propertyPACKAGE_PIN AL8 [get_ports "DDR4_A3"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A3"] ;
set_propertyPACKAGE_PIN AK10 [get_ports "DDR4_A4"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A4"] ;
set_propertyPACKAGE_PIN AH8 [get_ports "DDR4_A5"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A5"] ;
set_propertyPACKAGE_PIN AJ9 [get_ports "DDR4_A6"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A6"] ;
set_propertyPACKAGE_PIN AG8 [get_ports "DDR4_A7"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A7"] ;
set_propertyPACKAGE_PIN AH9 [get_ports "DDR4_A8"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A8"] ;
set_propertyPACKAGE_PIN AG10 [get_ports "DDR4_A9"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A9"] ;
set_propertyPACKAGE_PIN AH13 [get_ports "DDR4_A10"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A10"] ;
set_propertyPACKAGE_PIN AG9 [get_ports "DDR4_A11"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A11"] ;
set_propertyPACKAGE_PIN AM13 [get_ports "DDR4_A12"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A12"] ;
set_propertyPACKAGE_PIN AF8 [get_ports "DDR4_A13"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A13"] ;
set_propertyPACKAGE_PIN AC12 [get_ports "DDR4_A14_WE_B"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A14_WE_B"] ;
set_propertyPACKAGE_PIN AE12 [get_ports "DDR4_A15_CAS_B"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A15_CAS_B"] ;
set_propertyPACKAGE_PIN AF11 [get_ports "DDR4_A16_RAS_B"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_A16_RAS_B"] ;
set_propertyPACKAGE_PIN AK8 [get_ports "DDR4_BA0"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_BA0"] ;
set_propertyPACKAGE_PIN AL12 [get_ports "DDR4_BA1"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_BA1"] ;
set_propertyPACKAGE_PIN AE14 [get_ports "DDR4_BG0"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_BG0"] ;
set_propertyPACKAGE_PIN AB13 [get_ports "DDR4_CKE"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_CKE"] ;
set_propertyPACKAGE_PIN AJ11 [get_ports "DDR4_CK_C"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_CK_C"] ;
set_propertyPACKAGE_PIN AH11 [get_ports "DDR4_CK_T"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_CK_T"] ;
set_propertyPACKAGE_PIN AC13 [get_ports "DDR4_PAR"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_PAR"] ;
set_propertyPACKAGE_PIN AD14 [get_ports "DDR4_ACT_B"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_ACT_B"] ;
set_propertyPACKAGE_PIN AF10 [get_ports "DDR4_ODT"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_ODT"] ;
set_propertyPACKAGE_PIN AF12 [get_ports "DDR4_RESET_B"] ;
set_propertyIOSTANDARD LVCMOS12 [get_ports "DDR4_RESET_B"] ;
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