Xilinx ZCU106

ZCU106 Board User Guide 133
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Appendix B: Master Constraints File Listing
set_propertyPACKAGE_PIN AD12 [get_ports "DDR4_CS_B"] ;
set_propertyIOSTANDARD SSTL12 [get_ports "DDR4_CS_B"] ;
set_propertyPACKAGE_PIN AH18 [get_ports "DDR4_DM0"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM0"] ;
set_propertyPACKAGE_PIN AD15 [get_ports "DDR4_DM1"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM1"] ;
set_propertyPACKAGE_PIN AM16 [get_ports "DDR4_DM2"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM2"] ;
set_propertyPACKAGE_PIN AP18 [get_ports "DDR4_DM3"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM3"] ;
set_propertyPACKAGE_PIN AE18 [get_ports "DDR4_DM4"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM4"] ;
set_propertyPACKAGE_PIN AH22 [get_ports "DDR4_DM5"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM5"] ;
set_propertyPACKAGE_PIN AL20 [get_ports "DDR4_DM6"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM6"] ;
set_propertyPACKAGE_PIN AP19 [get_ports "DDR4_DM7"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DM7"] ;
set_propertyPACKAGE_PIN AF16 [get_ports "DDR4_DQ0"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ0"] ;
set_propertyPACKAGE_PIN AF18 [get_ports "DDR4_DQ1"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ1"] ;
set_propertyPACKAGE_PIN AG15 [get_ports "DDR4_DQ2"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ2"] ;
set_propertyPACKAGE_PIN AF17 [get_ports "DDR4_DQ3"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ3"] ;
set_propertyPACKAGE_PIN AF15 [get_ports "DDR4_DQ4"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ4"] ;
set_propertyPACKAGE_PIN AG18 [get_ports "DDR4_DQ5"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ5"] ;
set_propertyPACKAGE_PIN AG14 [get_ports "DDR4_DQ6"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ6"] ;
set_propertyPACKAGE_PIN AE17 [get_ports "DDR4_DQ7"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ7"] ;
set_propertyPACKAGE_PIN AA14 [get_ports "DDR4_DQ8"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ8"] ;
set_propertyPACKAGE_PIN AC16 [get_ports "DDR4_DQ9"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ9"] ;
set_propertyPACKAGE_PIN AB15 [get_ports "DDR4_DQ10"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ10"] ;
set_propertyPACKAGE_PIN AD16 [get_ports "DDR4_DQ11"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ11"] ;
set_propertyPACKAGE_PIN AB16 [get_ports "DDR4_DQ12"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ12"] ;
set_propertyPACKAGE_PIN AC17 [get_ports "DDR4_DQ13"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ13"] ;
set_propertyPACKAGE_PIN AB14 [get_ports "DDR4_DQ14"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ14"] ;
set_propertyPACKAGE_PIN AD17 [get_ports "DDR4_DQ15"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ15"] ;
set_propertyPACKAGE_PIN AJ16 [get_ports "DDR4_DQ16"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ16"] ;
set_propertyPACKAGE_PIN AJ17 [get_ports "DDR4_DQ17"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ17"] ;
set_propertyPACKAGE_PIN AL15 [get_ports "DDR4_DQ18"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ18"] ;
set_propertyPACKAGE_PIN AK17 [get_ports "DDR4_DQ19"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ19"] ;
set_propertyPACKAGE_PIN AJ15 [get_ports "DDR4_DQ20"] ;
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