Xilinx ZCU106

ZCU106 Board User Guide 134
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Appendix B: Master Constraints File Listing
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ20"] ;
set_propertyPACKAGE_PIN AK18 [get_ports "DDR4_DQ21"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ21"] ;
set_propertyPACKAGE_PIN AL16 [get_ports "DDR4_DQ22"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ22"] ;
set_propertyPACKAGE_PIN AL18 [get_ports "DDR4_DQ23"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ23"] ;
set_propertyPACKAGE_PIN AP13 [get_ports "DDR4_DQ24"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ24"] ;
set_propertyPACKAGE_PIN AP16 [get_ports "DDR4_DQ25"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ25"] ;
set_propertyPACKAGE_PIN AP15 [get_ports "DDR4_DQ26"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ26"] ;
set_propertyPACKAGE_PIN AN16 [get_ports "DDR4_DQ27"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ27"] ;
set_propertyPACKAGE_PIN AN13 [get_ports "DDR4_DQ28"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ28"] ;
set_propertyPACKAGE_PIN AM18 [get_ports "DDR4_DQ29"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ29"] ;
set_propertyPACKAGE_PIN AN17 [get_ports "DDR4_DQ30"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ30"] ;
set_propertyPACKAGE_PIN AN18 [get_ports "DDR4_DQ31"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ31"] ;
set_propertyPACKAGE_PIN AB19 [get_ports "DDR4_DQ32"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ32"] ;
set_propertyPACKAGE_PIN AD19 [get_ports "DDR4_DQ33"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ33"] ;
set_propertyPACKAGE_PIN AC18 [get_ports "DDR4_DQ34"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ34"] ;
set_propertyPACKAGE_PIN AC19 [get_ports "DDR4_DQ35"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ35"] ;
set_propertyPACKAGE_PIN AA20 [get_ports "DDR4_DQ36"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ36"] ;
set_propertyPACKAGE_PIN AE20 [get_ports "DDR4_DQ37"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ37"] ;
set_propertyPACKAGE_PIN AA19 [get_ports "DDR4_DQ38"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ38"] ;
set_propertyPACKAGE_PIN AD20 [get_ports "DDR4_DQ39"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ39"] ;
set_propertyPACKAGE_PIN AF22 [get_ports "DDR4_DQ40"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ40"] ;
set_propertyPACKAGE_PIN AH21 [get_ports "DDR4_DQ41"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ41"] ;
set_propertyPACKAGE_PIN AG19 [get_ports "DDR4_DQ42"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ42"] ;
set_propertyPACKAGE_PIN AG21 [get_ports "DDR4_DQ43"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ43"] ;
set_propertyPACKAGE_PIN AE24 [get_ports "DDR4_DQ44"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ44"] ;
set_propertyPACKAGE_PIN AG20 [get_ports "DDR4_DQ45"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ45"] ;
set_propertyPACKAGE_PIN AE23 [get_ports "DDR4_DQ46"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ46"] ;
set_propertyPACKAGE_PIN AF21 [get_ports "DDR4_DQ47"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ47"] ;
set_propertyPACKAGE_PIN AL22 [get_ports "DDR4_DQ48"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ48"] ;
set_propertyPACKAGE_PIN AJ22 [get_ports "DDR4_DQ49"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ49"] ;
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