Xilinx ZCU106

ZCU106 Board User Guide 135
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Appendix B: Master Constraints File Listing
set_propertyPACKAGE_PIN AL23 [get_ports "DDR4_DQ50"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ50"] ;
set_propertyPACKAGE_PIN AJ21 [get_ports "DDR4_DQ51"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ51"] ;
set_propertyPACKAGE_PIN AK20 [get_ports "DDR4_DQ52"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ52"] ;
set_propertyPACKAGE_PIN AJ19 [get_ports "DDR4_DQ53"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ53"] ;
set_propertyPACKAGE_PIN AK19 [get_ports "DDR4_DQ54"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ54"] ;
set_propertyPACKAGE_PIN AJ20 [get_ports "DDR4_DQ55"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ55"] ;
set_propertyPACKAGE_PIN AP22 [get_ports "DDR4_DQ56"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ56"] ;
set_propertyPACKAGE_PIN AN22 [get_ports "DDR4_DQ57"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ57"] ;
set_propertyPACKAGE_PIN AP21 [get_ports "DDR4_DQ58"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ58"] ;
set_propertyPACKAGE_PIN AP23 [get_ports "DDR4_DQ59"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ59"] ;
set_propertyPACKAGE_PIN AM19 [get_ports "DDR4_DQ60"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ60"] ;
set_propertyPACKAGE_PIN AM23 [get_ports "DDR4_DQ61"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ61"] ;
set_propertyPACKAGE_PIN AN19 [get_ports "DDR4_DQ62"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ62"] ;
set_propertyPACKAGE_PIN AN23 [get_ports "DDR4_DQ63"] ;
set_propertyIOSTANDARD POD12_DCI [get_ports "DDR4_DQ63"] ;
set_propertyPACKAGE_PIN AJ14 [get_ports "DDR4_DQS0_C"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS0_C"] ;
set_propertyPACKAGE_PIN AH14 [get_ports "DDR4_DQS0_T"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS0_T"] ;
set_propertyPACKAGE_PIN AA15 [get_ports "DDR4_DQS1_C"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS1_C"] ;
set_propertyPACKAGE_PIN AA16 [get_ports "DDR4_DQS1_T"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS1_T"] ;
set_propertyPACKAGE_PIN AK14 [get_ports "DDR4_DQS2_C"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS2_C"] ;
set_propertyPACKAGE_PIN AK15 [get_ports "DDR4_DQS2_T"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS2_T"] ;
set_propertyPACKAGE_PIN AN14 [get_ports "DDR4_DQS3_C"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS3_C"] ;
set_propertyPACKAGE_PIN AM14 [get_ports "DDR4_DQS3_T"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS3_T"] ;
set_propertyPACKAGE_PIN AB18 [get_ports "DDR4_DQS4_C"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS4_C"] ;
set_propertyPACKAGE_PIN AA18 [get_ports "DDR4_DQS4_T"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS4_T"] ;
set_propertyPACKAGE_PIN AG23 [get_ports "DDR4_DQS5_C"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS5_C"] ;
set_propertyPACKAGE_PIN AF23 [get_ports "DDR4_DQS5_T"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS5_T"] ;
set_propertyPACKAGE_PIN AK23 [get_ports "DDR4_DQS6_C"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS6_C"] ;
set_propertyPACKAGE_PIN AK22 [get_ports "DDR4_DQS6_T"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS6_T"] ;
set_propertyPACKAGE_PIN AN21 [get_ports "DDR4_DQS7_C"] ;
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS7_C"] ;
set_propertyPACKAGE_PIN AM21 [get_ports "DDR4_DQS7_T"] ;
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