Xilinx ZCU106

ZCU106 Board User Guide 136
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Appendix B: Master Constraints File Listing
set_propertyIOSTANDARD DIFF_POD12[get_ports "DDR4_DQS7_T"] ;
#QSPI
#QSPI_LWR U119 and UPR U120 are connected to PS MIO Bank 500
#Other net PACKAGE_PIN A24 - MIO0_QSPI_LWR_CLK Bank 500 - PS_MIO0
#Other net PACKAGE_PIN C24 - MIO1_QSPI_LWR_DQ1 Bank 500 - PS_MIO1
#Other net PACKAGE_PIN B24 - MIO2_QSPI_LWR_DQ2 Bank 500 - PS_MIO2
#Other net PACKAGE_PIN E25 - MIO3_QSPI_LWR_DQ3 Bank 500 - PS_MIO3
#Other net PACKAGE_PIN A25 - MIO4_QSPI_LWR_DQ0 Bank 500 - PS_MIO4
#Other net PACKAGE_PIN D25 - MIO5_QSPI_LWR_CS_B Bank 500 - PS_MIO5
#Other net PACKAGE_PIN B25 - MIO7_QSPI_UPR_CS_B Bank 500 - PS_MIO7
#Other net PACKAGE_PIN D26 - MIO8_QSPI_UPR_DQ0 Bank 500 - PS_MIO8
#Other net PACKAGE_PIN C26 - MIO9_QSPI_UPR_DQ1 Bank 500 - PS_MIO9
#Other net PACKAGE_PIN F26 - MIO10_QSPI_UPR_DQ2 Bank 500 - PS_MIO10
#Other net PACKAGE_PIN B26 - MIO11_QSPI_UPR_DQ3 Bank 500 - PS_MIO11
#Other net PACKAGE_PIN C27 - MIO12_QSPI_UPR_CLK Bank 500 - PS_MIO12
#FMC
#HPC0 J5
set_propertyPACKAGE_PIN E14 [get_ports "FMC_HPC0_CLK0_M2C_N"] ;
set_propertyIOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_N"] ;
set_propertyPACKAGE_PIN E15 [get_ports "FMC_HPC0_CLK0_M2C_P"] ;
set_propertyIOSTANDARD LVDS [get_ports "FMC_HPC0_CLK0_M2C_P"] ;
set_propertyPACKAGE_PIN F10 [get_ports "FMC_HPC0_CLK1_M2C_N"] ;
set_propertyIOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_N"] ;
set_propertyPACKAGE_PIN G10 [get_ports "FMC_HPC0_CLK1_M2C_P"] ;
set_propertyIOSTANDARD LVDS [get_ports "FMC_HPC0_CLK1_M2C_P"] ;
set_propertyPACKAGE_PIN V7 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"] ;
set_propertyPACKAGE_PIN V8 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"] ;
set_propertyPACKAGE_PIN T7 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"] ;
set_propertyPACKAGE_PIN T8 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"] ;
set_propertyPACKAGE_PIN R5 [get_ports "FMC_HPC0_DP0_C2M_N"] ;
set_propertyPACKAGE_PIN R6 [get_ports "FMC_HPC0_DP0_C2M_P"] ;
set_propertyPACKAGE_PIN R1 [get_ports "FMC_HPC0_DP0_M2C_N"] ;
set_propertyPACKAGE_PIN R2 [get_ports "FMC_HPC0_DP0_M2C_P"] ;
set_propertyPACKAGE_PIN T3 [get_ports "FMC_HPC0_DP1_C2M_N"] ;
set_propertyPACKAGE_PIN T4 [get_ports "FMC_HPC0_DP1_C2M_P"] ;
set_propertyPACKAGE_PIN U1 [get_ports "FMC_HPC0_DP1_M2C_N"] ;
set_propertyPACKAGE_PIN U2 [get_ports "FMC_HPC0_DP1_M2C_P"] ;
set_propertyPACKAGE_PIN N5 [get_ports "FMC_HPC0_DP2_C2M_N"] ;
set_propertyPACKAGE_PIN N6 [get_ports "FMC_HPC0_DP2_C2M_P"] ;
set_propertyPACKAGE_PIN P3 [get_ports "FMC_HPC0_DP2_M2C_N"] ;
set_propertyPACKAGE_PIN P4 [get_ports "FMC_HPC0_DP2_M2C_P"] ;
set_propertyPACKAGE_PIN U5 [get_ports "FMC_HPC0_DP3_C2M_N"] ;
set_propertyPACKAGE_PIN U6 [get_ports "FMC_HPC0_DP3_C2M_P"] ;
set_propertyPACKAGE_PIN V3 [get_ports "FMC_HPC0_DP3_M2C_N"] ;
set_propertyPACKAGE_PIN V4 [get_ports "FMC_HPC0_DP3_M2C_P"] ;
set_propertyPACKAGE_PIN H3 [get_ports "FMC_HPC0_DP4_C2M_N"] ;
set_propertyPACKAGE_PIN H4 [get_ports "FMC_HPC0_DP4_C2M_P"] ;
set_propertyPACKAGE_PIN G1 [get_ports "FMC_HPC0_DP4_M2C_N"] ;
set_propertyPACKAGE_PIN G2 [get_ports "FMC_HPC0_DP4_M2C_P"] ;
set_propertyPACKAGE_PIN L5 [get_ports "FMC_HPC0_DP5_C2M_N"] ;
set_propertyPACKAGE_PIN L6 [get_ports "FMC_HPC0_DP5_C2M_P"] ;
set_propertyPACKAGE_PIN L1 [get_ports "FMC_HPC0_DP5_M2C_N"] ;
set_propertyPACKAGE_PIN L2 [get_ports "FMC_HPC0_DP5_M2C_P"] ;
set_propertyPACKAGE_PIN M3 [get_ports "FMC_HPC0_DP6_C2M_N"] ;
set_propertyPACKAGE_PIN M4 [get_ports "FMC_HPC0_DP6_C2M_P"] ;
set_propertyPACKAGE_PIN N1 [get_ports "FMC_HPC0_DP6_M2C_N"] ;
set_propertyPACKAGE_PIN N2 [get_ports "FMC_HPC0_DP6_M2C_P"] ;
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