Name: Xilinx ZCU106
Brand: Xilinx
Rating: 4 (1 reviews)

ZCU106 Board User Guide 144

UG1244 (v1.0) March 28, 2018 www.xilinx.com

Appendix B: Master Constraints File Listing

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_1_LS"] ;

set_property PACKAGE_PIN AP11 [get_ports "PMOD1_2_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_2_LS"] ;

set_property PACKAGE_PIN AN11 [get_ports "PMOD1_3_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_3_LS"] ;

set_property PACKAGE_PIN AP9 [get_ports "PMOD1_4_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_4_LS"] ;

set_property PACKAGE_PIN AP10 [get_ports "PMOD1_5_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_5_LS"] ;

set_property PACKAGE_PIN AP12 [get_ports "PMOD1_6_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_6_LS"] ;

set_property PACKAGE_PIN AN12 [get_ports "PMOD1_7_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_7_LS"] ;

#PROTOTYPE MALE PIN HEADER 2X12

set_property PACKAGE_PIN K13 [get_ports "L6N_AD6N_64_N"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "L6N_AD6N_64_N"] ;

set_property PACKAGE_PIN L14 [get_ports "L6P_AD6P_64_P"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "L6P_AD6P_64_P"] ;

set_property PACKAGE_PIN J14 [get_ports "L5N_AD14N_64_N"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "L5N_AD14N_64_N"] ;

set_property PACKAGE_PIN K14 [get_ports "L5P_AD14P_64_P"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "L5P_AD14P_64_P"] ;

set_property PACKAGE_PIN J11 [get_ports "L4N_AD7N_64_N"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "L4N_AD7N_64_N"] ;

set_property PACKAGE_PIN K12 [get_ports "L4P_AD7P_64_P"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "L4P_AD7P_64_P"] ;

set_property PACKAGE_PIN L11 [get_ports "L3N_AD15N_64_N"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "L3N_AD15N_64_N"] ;

set_property PACKAGE_PIN L12 [get_ports "L3P_AD15P_64_P"] ;

set_property IOSTANDARD LVCMOS18 [get_ports "L3P_AD15P_64_P"] ;

set_property PACKAGE_PIN G24 [get_ports "L14N_HDGC_65_N"] ;

set_property IOSTANDARD LVDS [get_ports "L14N_HDGC_65_N"] ;

set_property PACKAGE_PIN G23 [get_ports "L14P_HDGC_65_P"] ;

set_property IOSTANDARD LVDS [get_ports "L14P_HDGC_65_P"] ;

#MSP430 SYSTEM CONTROLLER

set_property PACKAGE_PIN J6 [get_ports "MSP430_GPIO_PL_0"] ;

set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_0"] ;

set_property PACKAGE_PIN J7 [get_ports "MSP430_GPIO_PL_1"] ;

set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_1"] ;

set_property PACKAGE_PIN J9 [get_ports "MSP430_GPIO_PL_2"] ;

set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_2"] ;

set_property PACKAGE_PIN K9 [get_ports "MSP430_GPIO_PL_3"] ;

set_property IOSTANDARD LVCMOS33 [get_ports "MSP430_GPIO_PL_3"] ;

set_property PACKAGE_PIN AA17 [get_ports "MSP430_UCA1_TXD_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "MSP430_UCA1_TXD_LS"] ;

set_property PACKAGE_PIN AH16 [get_ports "MSP430_UCA1_RXD_LS"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "MSP430_UCA1_RXD_LS"] ;

#SFP

#SFP0

set_property PACKAGE_PIN AE22 [get_ports "SFP0_TX_DISABLE"] ;

set_property IOSTANDARD LVCMOS12 [get_ports "SFP0_TX_DISABLE"] ;

set_property PACKAGE_PIN AA1 [get_ports "SFP0_RX_N"] ;

set_property PACKAGE_PIN AA2 [get_ports "SFP0_RX_P"] ;

set_property PACKAGE_PIN Y3 [get_ports "SFP0_TX_N"] ;

set_property PACKAGE_PIN Y4 [get_ports "SFP0_TX_P"] ;

set_property PACKAGE_PIN AE22 [get_ports "SFP0_TX_DISABLE"] ;

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English

Xilinx ZCU106 User Manual

Table of Contents

Other manuals for Xilinx ZCU106

Questions and Answers:

Xilinx ZCU106 Specifications

Related product manuals